Novel SPI-NAND Flash memory chip with DDR high transmission interface and operation method

Abstract

The invention discloses a novel SPINAND Flash storage chip with a high transmission interface. The novel SPINAND Flash storage chip comprises an SPI command logic control unit, an MCU digital logic unit, an NAND Flash storage unit and a DQS pin, wherein the SPI command logic control unit can be used for issuing an SPI command; the MCU digital logic unit comprises a DDR Ping buffer and a DDR Pong buffer. Wherein the NAND Flash storage unit comprises a static random access memory and an NAND flash memory, and the static random access memory comprises a data buffer and a register; wherein the DQSpin exchanges signals with the SPI command logic control unit, the MCU digital logic unit exchanges signals with the NAND Flash storage unit, and a DDR mode is built in the MCU digital logic unit, sothat the DQS pin reads data of the NAND Flash storage unit; data are loaded into a data buffer according to an SPI command issued by an SPI command logic control unit, a DDR command is started downwards to start a DQS to serve as a synchronizing signal Clock, and the data are read through signals of the Clock and the DQS.

Description

technical field [0001] The invention belongs to the technical field of memory chips, and in particular relates to a novel SPI-NAND Flash memory chip with a DDR high transmission interface. Background technique [0002] At present, the clock frequency of the SPI-NAND Flash chip is about 104Mhz~120Mhz, and the data throughput of the four channels is about 480Mbit / S. In order to meet the needs of high-speed transmission, it refers to the NV-DDR2 (Double Data Rate) mode in the Open NAND Flash Interface Specification Adding the basics to SPI-NAND Flash will increase the maximum throughput by 2 times to 960Mbit / S. [0003] In the synchronous (Synchronous) mode of operation, the current highest channel of the existing SPI-NAND Flash chip is I / O of 4Bit, while the highest channel of TSOP SLC Parallel NAND Flash is 8Bit of I / O, so the overall throughput will increase. 2x difference. [0004] SPI-NAND is currently a standard component and has been applied to various system platforms...

AI Technical Summary

Problems solved by technology

[0005] 1. With the current standard component packaging specifications of WSON8, MLC (Multi-level cell) Flash chips must be used to support medium and high capacity, and MLC NAND Flash Die Size (chip size) cannot be packaged in WSON8 due to the increase in capacity in the specification;

[0006] 2. Using the DDR2 specification will increase the transmission throughput by 2 times, but the current WSON8 cannot support the DDR2 specification. The reason is that the number of buses is only 8 Pins, but if it is necessary to increase the control lines required by DDR2, it needs Modify the number of buses

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