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High-speed ADC error calibration circuit

An error calibration and high-speed technology, applied in the field of analog-to-digital conversion integrated circuits, can solve the problems of data acquisition accuracy and speed impact, circuit accuracy degradation, and sampling time cannot be very long, etc.

Pending Publication Date: 2021-03-16
HEFEI AICHUANGWEI ELECTRONIC TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The process of capacitor charging is a transient process, which causes the voltage on the capacitor not to reach the voltage to be maintained immediately, but takes a certain period of time. The longer the time, the closer to the ideal voltage value, but the actual sampling time It cannot be very long, it will be affected by the accuracy and speed of data collection
The sampling voltage error is large, resulting in a decrease in the overall circuit accuracy
This technology is not suitable for the occasion of high-speed conversion of this project

Method used

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  • High-speed ADC error calibration circuit

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Embodiment Construction

[0012] The following will be described in conjunction with the non-limiting embodiments of the present invention and the accompanying drawings.

[0013] The schematic diagram of the dynamic comparator is shown in figure 1 shown. When the value of Φc is low, the comparator is in the reset phase. When the Φc value is high, the comparator is in the conversion phase. The preamplifier is placed before the comparator to suppress playback noise. Background offset calibration is achieved by placing an auxiliary differential pair, one of which fixes the gate voltage and the other regulates the gate voltage through a negative feedback loop. In order to cancel the switching noise on 'Vcm', the bottom plate of the CT is connected to 'Vcm'. Also, a latch follows outp and outn to store the comparison result. When the differential input of the preamplifier is shorted, the calibration stage is placed after the last comparison.

[0014] The entire ADC architecture as image 3 As shown, ...

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Abstract

The invention belongs to the field of analog-to-digital conversion integrated circuits, and is characterized in that a high-speed ADC error calibration circuit is invented to compensate and calibratethe input offset of a preset amplifier and a comparator without influencing the normal work of the whole ADC. According to the invention, a sampling circuit capable of reducing clock phase offset andrealizing high-speed ADC error calibration is adopted. According to the circuit structure, a differential pair is additionally arranged at the input end of the amplifier, one end is fixed, and the other end is adjusted to compensate offset voltage. A back-end automatic compensation loop is established, and offset compensation is embedded in a normal analog-to-digital conversion process. The sampling circuit can be widely applied to a time-interleaved ADC, and a traditional multi-phase clock generation circuit based on a delay locked loop (DLL) can be avoided.

Description

technical field [0001] The invention belongs to the field of analog-to-digital conversion integrated circuits, and is characterized in that a high-speed ADC error calibration circuit is invented to compensate and calibrate the input offset of a preset amplifier and a comparator without affecting the normal operation of the entire ADC. Background technique [0002] ADCs are widely used in data acquisition systems, automatic test equipment (ATE), medical instruments, monitoring equipment, laboratory instruments, and programmable logic controllers (PLC) and other fields, and are an important bridge between analog and digital systems. High-speed ADC has become an important link in determining the performance of modern electronic equipment such as radar, communication, electronic countermeasures, aerospace, missiles, measurement and control, ground development, medical treatment, instrumentation, images, high-performance controllers and digital communication systems. Due to the i...

Claims

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Application Information

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IPC IPC(8): H03M1/10H03M1/06H03M1/12
CPCH03M1/0617H03M1/1009H03M1/1245
Inventor 潘俊季芬芬王威
Owner HEFEI AICHUANGWEI ELECTRONIC TECH CO LTD