Resistive random access memory structure and manufacturing method thereof

Abstract

The present invention provides a resistive random access memory structure and a manufacturing method thereof. The resistive random access memory structure comprises: a substrate having an array regionand a peripheral region; a first low-dielectric-constant dielectric layer, which is located in the peripheral area and has a dielectric constant of smaller than 3; a plurality of memory cells, whichare positioned on the substrate and are positioned in the array region; a gap filling dielectric layer, which is located in the array region, covers the memory cells and fills in space between the adjacent memory cells; a plurality of first conductive plugs, which are located in the gap filling dielectric layer, wherein each of the first conductive plugs is in contact with one of the memory cells;and a dummy memory unit, which is located at the junction of the array region and the peripheral region and is not in contact with any one of the first conductive plugs. According to the resistive random access memory structure provided by the invention, the yield and the reliability of a product can be obviously improved, and process complexity, production cost and production time are reduced.

Description

technical field [0001] The invention relates to a storage device, in particular to a resistive random access storage structure and a manufacturing method thereof. Background technique [0002] Resistive random access memory (RRAM) has the advantages of simple structure, small area, low operating voltage, fast operating speed, long memory time, multi-state memory, and low power consumption. Therefore, the resistive random access memory has great potential to replace the current flash memory and become the mainstream of the next generation non-volatile memory. [0003] In known RRAMs, a chip usually includes an array area and a peripheral area. The array area includes a plurality of memory cells, and each memory cell includes a patterned bottom electrode layer, a resistance transition layer and a top electrode layer. The peripheral area is mainly logic circuits. In the peripheral area, in order to increase the operating speed of the logic circuit, the dielectric layer uses ...

AI Technical Summary

Problems solved by technology

When a low-k dielectric material is formed between a plurality of memory cells, due to the poor gap filling ability of the low-k dielectric material, holes will be generated between the plurality of memory cells

As a result, the operation of the resistive random access memory device is prone to errors, and the yield and reliability of the product are deteriorated

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