FPGA code stream data verification method and device

Abstract

The invention relates to an FPGA code stream data verification method and device. By combining checksum check and row-column CRC cross check, on the basis of ensuring the integrity and accuracy of the code stream data, whether the code stream data has errors in the processing, transmission and storage processes or not is effectively detected, the error positions can be quickly found, then error correction processing is carried out, and the self-error-correction effect of the code stream data is achieved. Moreover, the code stream data is partitioned, and then cyclic redundancy check is performed on each code stream data block in parallel, so that the check speed is increased, and the reliability of FPGA design is improved.

Description

technical field [0001] The invention relates to the field of FPGA development, in particular to an FPGA code stream data verification method and an FPGA code stream data verification device. Background technique [0002] The development of FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) usually includes processes such as RTL (register transfer level) design, function simulation, logic synthesis, layout and routing, and board-level verification. The code stream data in binary format will be generated, and the code stream data will be downloaded to the corresponding FPGA chip according to the timing requirements of the device, so that specific functions can be realized. [0003] Whether the code stream data information is correct or not directly determines whether the function of the chip is correct. However, the code stream data may change during processing, storage and transmission. For example, if one or several data bits are wrong, if it is direc...

AI Technical Summary

Problems solved by technology

However, the code stream data may change during processing, storage and transmission. For example, if one or several data bits are wrong, if it is directly used to realize the function of the chip, the chip may not work normally, or even produce unpredictable consequences. , therefore, it is necessary to check in time whether there is an error in the code stream data written to the FPGA chip during storage and transmission, and to correct the error in time when an error occurs, so as to avoid abnormal operation of the FPGA chip due to code stream data errors

[0004] The existing verification method for code stream data can only confirm that there is a problem with the data written into the chip at the time, but cannot confirm the problem location, nor can it directly correct the error. It can only be resent by the sender to try to solve the problem, which takes a long time and is also Not conducive to subsequent improvement

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