A FPGA Implementation Method of Multiple Types of Convolution

Abstract

The present invention provides an FPGA implementation method of multiple types of convolutions, which can utilize a unified hardware architecture to deploy multiple types of convolutions on the FPGA for implementation, without the need to separately design hardware implementation architectures for different types of convolutions, Save a lot of hardware resources. By analyzing the characteristics of multiple types of convolutions, they are converted into the same benchmark convolution type and implemented using a unified processing engine. Compared to implementing these convolutions separately on the FPGA, a lot of hardware resources are saved. By optimizing the operation process of the benchmark convolution, and according to the characteristics of the remaining convolutions, they are respectively converted into benchmark convolutions for operation. Therefore, it can be realized on FPGA using a unified hardware architecture. The flexibility of implementation is improved, the overhead of hardware resources is reduced, and the problems of large resource consumption and inflexible structure caused by the need to separately design and implement architectures for various types of convolutions in the traditional FPGA implementation method are effectively avoided.

Description

technical field [0001] The invention belongs to the technical field of image detection and recognition, and in particular relates to an FPGA implementation method of multiple types of convolutions. Background technique [0002] In the past five years, deep neural networks have made breakthroughs in the field of intelligent image processing and have a wide range of application scenarios. There are a large number of network weight parameters and calculations in deep convolutional neural networks, so most deep neural network algorithms are currently deployed on high-performance devices such as CPU or GPU. However, the high performance of CPU and GPU requires a lot of power consumption support, so it is difficult to apply in some application scenarios where power consumption is strictly limited. High-performance, low-power embedded hardware devices provide a new solution to this problem. Therefore, building a deep neural network implementation platform based on embedded devices...

AI Technical Summary

Problems solved by technology

However, in some application scenarios, the performance requirements for image feature extraction, detection and recognition are constantly improving, the deep neural network structure used is becoming more and more complex, and the convolution type involved in the network has also changed from a single type at the beginning. It is rich and needs to design and implement architectures for each type of convolution separately. However, FPGA on-chip logic and storage resources are limited, and it is difficult to design and implement structures for each type of convolution separately, so that this type of deep neural network that includes multiple types of convolutions can be implemented on FPGA. There are certain technical difficulties in the network

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