A manufacturing method of a display backplane, a display backplane and a display device
A display backplane and manufacturing method technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of high leakage current of switching transistors and increased power consumption of display backplanes, so as to reduce power consumption and The effect of leakage current
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Embodiment 1
[0061] refer to figure 1 , showing a flowchart of a method for manufacturing a display backplane according to an embodiment of the present invention, which may specifically include the following steps:
[0062] Step 101, forming a first active layer and a second active layer on a base substrate; the materials of the first active layer and the second active layer are oxide semiconductors, and the first active layer is layer has a first channel region and a first non-channel region located on both sides of the first channel region, the second active layer has a second channel region and located on both sides of the second channel region the second non-channel region.
[0063] In this embodiment of the present invention, as figure 2 As shown, the base substrate 21 may be a rigid substrate, such as a glass substrate, etc., and the base substrate 21 may also be a flexible substrate, such as a PI (Polyimide, polyimide) substrate, and the like.
[0064] After the base substrate 2...
Embodiment 2
[0117] The embodiment of the present invention also provides a display backplane, which can be manufactured by using the manufacturing method of the display backplane described in the first embodiment. Specifically, the display backplane includes: a base substrate 21 ; a first active layer 22 and a second active layer 23 arranged on the base substrate 21 , the first active layer 22 and the second active layer 23 are The material is an oxide semiconductor, and the first active layer 22 has a first channel region 221 and a first non-channel region 222 on both sides of the first channel region 221, and the second active layer 23 has a second channel region 231 and the second non-channel region 232 on both sides of the second channel region 231; the first gate insulating layer 24 covering the first active layer 22 and the second active layer 23; provided on the first gate insulating layer The first gate 25 and the second gate 26 on 24, the orthographic projection of the first gate...
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