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Grid grounding field effect transistor for ESD protection circuit and preparation method of grid grounding field effect transistor

A technology of gate grounding and field effect transistors, which is applied to circuits, transistors, electrical components, etc., can solve the problems of reduced anti-ESD capabilities and achieve the effect of size reduction

Active Publication Date: 2021-06-25
JOULWATT TECH INC LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] However, in the process proposed in this patent, due to the reduction of the ballast resistance, the ESD resistance of the device is reduced. Therefore, it is necessary to improve the problems in the prior art to obtain better ESD protection at low cost. device

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  • Grid grounding field effect transistor for ESD protection circuit and preparation method of grid grounding field effect transistor
  • Grid grounding field effect transistor for ESD protection circuit and preparation method of grid grounding field effect transistor
  • Grid grounding field effect transistor for ESD protection circuit and preparation method of grid grounding field effect transistor

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no. 1 example

[0039] See figure 2, is a structural diagram of a grounded gate field effect transistor in the first embodiment of the present invention. As shown in the figure, in this embodiment, the gate-grounded field effect transistor used in the ESD protection circuit is a GGNMOS transistor, including a P-type substrate 10, a P-type well region 11 located on the P-type substrate 10, and a P-type well region 11 located on the P-type substrate 10. The gate 13 above the type deep well region 11, the source terminal 14 and the drain terminal 12 located in the well region, the source terminal 14 and the drain terminal 12 are located on both sides of the gate 13, and the source terminal 14 is located near the outside body end17. Generally, the gate 13 includes a gate oxide on the substrate 10 and a polysilicon gate on the gate oxide. The source terminal 14 , the drain terminal 12 and the body terminal 17 have a heavily doped region with a higher concentration than the P-type deep well regi...

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Abstract

The invention provides a grid grounding field effect transistor for an ESD protection circuit and a preparation method of the grid grounding field effect transistor. The drain end of the grid grounding field effect transistor comprises a first N-type heavily doped region close to a grid and a second N-type heavily doped region far away from the grid; an oxide isolation is arranged between the first N-type heavily doped region and the second N-type heavily doped region; a polycrystalline silicon resistor is arranged on the oxide isolation; and the first N-type heavily doped region and the second N-type heavily doped region are connected with the polycrystalline silicon resistor through wires. The external poly resistor is used for replacing a ballast resistor, a mask plate, namely a metal silicide barrier layer is omitted, and thus, the same ESD current discharge capacity can be achieved under the condition that the size of the device is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a gate grounding field effect transistor for an ESD protection circuit and a preparation method thereof. Background technique [0002] Electrostatic discharge (ESD: Electrostatic Discharge) should be the main culprit that causes all electronic components or integrated circuit systems to cause excessive electrical stress (EOS: Electrical Over Stress) damage. Because static electricity usually has a very high instantaneous voltage (> several thousand volts), this kind of damage is destructive and permanent, and will cause the circuit to burn directly. According to the statistics of the National-Semiconductor Corporation (National-Semiconductor), 38% of today's integrated circuit failure products are caused by ESD / EOS. [0003] In traditional designs, GGNMOS is often used as an ESD protection device, which is compatible with most CMOS processes. In the prior art, each pi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/08H01L29/78H01L27/02H01L23/48H01L21/336
CPCH01L29/0847H01L23/481H01L29/783H01L29/66477H01L27/0266
Inventor 胡涛王炜槐
Owner JOULWATT TECH INC LTD