Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the forming method comprises the steps: etching a fourth doped material layer, a second semiconductor material layer, a third doped material layer, a buffer material layer, a second doped material layer and a first semiconductor material layer, respectively forming a fourth doped layer, a second semiconductor column, a third doped layer, a buffer layer, a second doped layer and a first semiconductor column, wherein the conductive types of doped ions of the third doped layer and the second doped layer are different, and forming a first gate structure on the side wall of the first semiconductor column; and after the first gate structure is formed, forming a second gate structure on the side wall of the second semiconductor column. According to the embodiment of the invention, the buffer layer enables the third doped layer to be not in direct contact with the second doped layer, so that the doped ions in the second doped layer are not liable to diffuse into the third doped layer, the doped ions in the third doped layer are not liable to diffuse into the second doped layer, and the performance of the semiconductor structure is optimized.

Description

Technical field [0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method of forming thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving toward higher component density, and the direction of higher integration, the semiconductor process nodes will continue to decrease in the development trend of Moore's law. Transistors are currently being widely used as the most basic semiconductor device, so as the component density and integration of the semiconductor device increases, the channel length of the transistor is not shortened to adapt to the decrease of the process node. [0003] The shortening of the transistor channel length has the advantage of increasing the die density of the chip, increasing the switching speed. However, as the channel length is shortened, the distance between the transistor source a...

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Problems solved by technology

However, with the shortening of the channel length, the distance between the source and the drain of the transistor is also shortened, and the control ability of the gate to the channel becomes worse, resulting in the phenomenon of subthreshold leakage, the so-called short channel The short-channel effects (SCE) are more likely to occur, and the channel leakage current of the transistor increases

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