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Formation method of semiconductor structure

A semiconductor and graphics layer technology, applied in the field of semiconductor structure formation, can solve the problems of difficult channels and poor channel control ability of the gate structure, and achieve good shape quality, small side wall roughness, and improved The effect of electrical properties

Pending Publication Date: 2021-07-20
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the ability of the gate structure to control the channel becomes worse, and the gate voltage pinches off the channel. The difficulty of the channel is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (short-channel effects, SCE) more prone to occur

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Embodiment Construction

[0029] The devices currently formed have poor performance. The method of forming a semiconductor structure is a cause of poor performance.

[0030] Figure 1 to 4 It is a schematic structural diagram of each step in the method of forming a semiconductor structure.

[0031] Such as figure 1 As shown, a substrate is provided, the substrate comprising an initial substrate 1 and a core layer 2 located on the initial substrate 1.

[0032] Such as figure 2 As shown, the initial substrate 1 exposed at the core layer 2 and the core layer 2 is contained on the first side wall material layer, and the core layer 2 is removed and the initial substrate 1 is removed. The first side wall material layer is located on the remaining of the first side wall material layer on the side wall of the core layer 2 as the first side wall layer 3.

[0033] Combined reference image 3 After the first side wall layer 3 is formed, the core layer 2 is removed; the first side wall layer 3 and the initial substrate...

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Abstract

The invention discloses a forming method of a semiconductor structure. The forming method comprises the steps of providing a substrate; forming an initial pattern layer on the substrate; carrying out one or more atomic layer etching treatment on the side wall of the initial pattern layer to form a pattern layer, wherein the atomic layer etching treatment comprises the steps that an organic matter layer is formed on the side wall of the initial pattern layer; and the organic matter layer is removed. Generally, the bond energy between the atoms on the outermost surface of the side wall of the initial pattern layer and the atoms on the inner layer is smaller than the bond energy between the atoms on the inner layer, and the organic matter layer usually carries elements capable of reacting with the side wall of the initial pattern layer, so that the bond energy between the atoms on the outermost surface of the side wall of the initial pattern layer and the atoms on the inner layer is further reduced; in the process of removing the organic matter layer, atoms on the outermost surface of the side wall of the initial pattern layer can be stripped, so that after multiple atomic layer etching treatment, the protruding area on the side wall of the initial pattern layer is flattened, correspondingly, the roughness of the side wall of the formed pattern layer is small, and the electrical performance of the semiconductor structure can be improved.

Description

Technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and more particularly to a method of forming a semiconductor structure. Background technique [0002] In semiconductor manufacturing, with the development trend of large scale integrated circuits, the integrated circuit features continue to decrease, in order to adapt to smaller feature sizes, metal-oxide-semiconductor field-Effect Transistor The channel length of the MOSFET is also constantly shortened. However, as the length of the device channel length is shortened, the distance between the source and the drain is also shortened, so the control capability of the gate structure on the channel is deteriorated, and the gate voltage clamping groove. The difficulty of the road is also increasing, making the Subthreshold Leakage phenomenon, the so-called short-channel effects, SCE) more prone to occur. [0003] Therefore, in order to better adapt the feature size, the semi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/3065H01L21/311
CPCH01L29/66795H01L21/31138H01L21/3065H01L21/0337H01L21/31127H01L21/32136H01L21/823412
Inventor 张海洋刘盼盼杨晨曦
Owner SEMICON MFG INT (SHANGHAI) CORP