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Electrostatic discharge blocking circuit

An electrostatic discharge and circuit technology, applied in the direction of logic circuit coupling device, programmable logic circuit device, logic circuit connection/interface layout, etc., can solve problems such as integrated circuit damage

Pending Publication Date: 2021-07-23
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

General commercial integrated circuits must have a certain degree of HBM and MM tolerance before they can be sold, otherwise, the integrated circuit is very easy to be damaged due to accidental ESD events

Method used

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  • Electrostatic discharge blocking circuit
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Embodiment Construction

[0027] In order to make the objects, features and advantages of the present invention more obvious and easy to understand, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. The present specification provides different embodiments to illustrate the technical features of different embodiments of the present invention. Wherein, the configuration of each element in the embodiment is for illustration, and not for limiting the present invention. In addition, parts of the reference numerals in the drawings in the embodiments are repeated for the purpose of simplifying the description, and do not mean the correlation between different embodiments.

[0028] figure 1 It is a schematic diagram of the structure of the electrostatic discharge isolation circuit of the present invention. As shown, the ESD isolation circuit 100 includes an internal circuit 110 , a schottky diode 120 and an ESD discharge element 130 . The int...

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Abstract

The invention provides an electrostatic discharge blocking circuit. The electrostatic discharge blocking circuit comprises an internal circuit, a Schottky diode and an electrostatic discharge release element, wherein the Schottky diode is coupled between a specific node and the internal circuit; and the electrostatic discharge release element is coupled between the specific node and a power supply end. When an electrostatic discharge event occurs at the specific node, the electrostatic discharge release element is turned on to release an electrostatic discharge current from the specific node to the power supply end. An integrated circuit can be protected.

Description

technical field [0001] The present invention relates to an electrostatic discharge isolation circuit, in particular to an electrostatic discharge isolation circuit with electrostatic discharge discharge elements. Background technique [0002] An electrostatic discharge (ESD) event of an integrated circuit refers to a process of discharging electrostatic charges with a high voltage through an integrated circuit chip. Although the amount of such electrostatic charge is usually small, the instantaneous energy released by it is also considerable due to the high voltage. If it is not handled properly, the integrated circuit will often be burned. [0003] Therefore, ESD has been one of the important reliability considerations in semiconductor products. There are two types of ESD tests that are familiar to the general public, the human body model (HBM) and the machine model (MM). Generally, commercial integrated circuits must have a certain degree of HBM and MM tolerance before t...

Claims

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Application Information

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IPC IPC(8): H03K19/0175H03K19/003
CPCH03K19/003H03K19/00307H03K19/017545H03K19/017581
Inventor 周业宁李建兴黄绍璋林志轩邱华琦
Owner VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION