Packaging interconnection structure between chip and circuit board and chip packaging method
An interconnection structure and circuit board technology, applied in the directions of printed circuit, printed circuit, printed circuit manufacturing, etc., can solve the problems of increasing the transmission loss and enlargement of the chip and the circuit board, achieving flexible selection, reducing transmission loss, The effect of reducing transmission loss
Pending Publication Date: 2021-07-23
苏州硕贝德创新技术研究有限公司 +1
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Problems solved by technology
[0005] In order to solve the problem that when the diameter of the solder ball increases, the diameter of the metal pad also increases accordingly, resulting in a larger transition from the rewiring layer to the metal pad, which increases the transmission loss between the chip and the circuit board. The following embodiments disclose the packaging and interconnection structure between the chip and the circuit board, and the chip packaging method
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[0042] Packaging refers to the packaging of chips. When the solder ball is soldered to the pad, the RDL trace is connected to the pad. When the ball diameter increases, the pad diameter increases accordingly, and the transition from the RDL trace to the pad becomes larger. Usually the RDL line width does not exceed 50um, and the diameter of the pad is in the range of 200-500um. The discontinuity introduced will cause impedance mismatch. As the size of the solder ball increases, it will cause an increase in transmission loss.
[0043] In order to solve the problem that when the diameter of the solder ball increases, the diameter of the metal pad also increases accordingly, resulting in a larger transition from the rewiring layer to the metal pad, which increases the transmission loss between the chip and the circuit board. The following embodiments disclose the packaging interconnection structure between the chip and the circuit board, and the chip packaging method.
[0044] ...
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The invention discloses a packaging interconnection structure between a chip and a circuit board and a chip packaging method. A first hollow structure is arranged on a second wiring layer in a rewiring layer, a second hollow structure is arranged on a third wiring layer, and a third hollow structure is arranged on a circuit board line layer of a circuit board. Thus, the area of the second wiring layer, the area of the third wiring layer and the area of the circuit board line layer are reduced, the capacitance between different layers is effectively restrained, and the transmission loss is reduced. When a solder ball with a large diameter needs to be used for welding, the transmission loss is reduced through the hollow structures, so that the selection of the ball diameter of the solder ball in practical application is more flexible.
Description
technical field [0001] The present application relates to the technical field of chip packaging, in particular to a packaging interconnection structure between a chip and a circuit board, and a chip packaging method. Background technique [0002] Wafer level packaging (WLP) is a technology that takes wafers as the processing object, completes all packaging and testing of multiple chips on the wafer at the same time, and then slices and divides them. WLP introduces a redistribution layer (RDL), adopts a standard patch process, and the chip (IC) is connected to the circuit board (PCB) face down, and has good electrical performance. [0003] The rewiring layer coats an insulating protective layer on the chip, then defines a new wire pattern by exposure and development, and then uses electroplating technology to make new metal lines to achieve the purpose of line redistribution. The redistribution layer includes metal pads on which solder balls are soldered, and then the chip c...
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IPC IPC(8): H05K1/02H05K1/11H05K1/18H05K3/30
CPCH05K1/0298H05K1/111H05K1/181H05K3/303H05K2201/09072
Inventor 钱占一李琴芳俞斌
Owner 苏州硕贝德创新技术研究有限公司