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Method for forming interconnection structure

A technology of interconnect structure and barrier layer, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of high cost and cumbersome process, and achieve the effects of reducing warpage, simplifying process and reducing material consumption

Pending Publication Date: 2021-07-30
GUANGZHOU CANSEMI TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The object of the present invention is to provide a method for forming an interconnection structure, so as to solve the above-mentioned problems of cumbersome process and high cost in the process of forming the interconnection structure

Method used

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  • Method for forming interconnection structure

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Embodiment Construction

[0033] In order to make the purpose, advantages and features of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in very simplified form and not drawn to scale, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention. In addition, the structures shown in the drawings are often a part of the actual structure. In particular, each drawing needs to display different emphases, and sometimes uses different scales.

[0034] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is usually used in the sense of including "and / or", and the term "several" Usually, the term "at least one" is used in the meaning of "at least one", and the term "at least two" is usually used in the meaning of "two or more". In a...

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Abstract

The invention provides a method for forming an interconnection structure, which comprises the following steps of: providing a substrate, forming a dielectric layer on the surface of the substrate, and forming a through hole for exposing the surface of the substrate in the dielectric layer; sequentially forming an adhesion layer and a barrier layer, the adhesion layer covering the dielectric layer and the inner wall of the through hole, and the barrier layer covering the adhesion layer; forming a first conductive layer, wherein the first conductive layer fills the through hole and covers the barrier layer; taking the barrier layer as a grinding stop layer, and executing a chemical mechanical grinding process; and forming a second conductive layer, the second conductive layer covering the barrier layer and the first conductive layer in the through hole. The barrier layer is used as the grinding stop layer of CMP, the adhesion layer and the barrier layer are formed only once, the forming method of the interconnection structure is simplified, the technological process can be shortened, and the cost is reduced; by simplifying the forming method and reducing the thickness required for forming the dielectric layer, the material consumption can be reduced, and meanwhile, the warping degree of the substrate can be reduced, so that the problems of tedious process and relatively high cost in the process of forming the interconnection structure are solved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a method for forming an interconnection structure. Background technique [0002] Metal oxide semiconductor (Metal Oxide Semiconductor, MOS) devices are widely used in portable electronic equipment, automotive electronics, industrial control, lighting and other fields due to their low price, mature technology, fast switching speed, simple driving and many other advantages. [0003] In the traditional technology, after filling tungsten in the through hole (contact hole), excess tungsten needs to be removed by chemical mechanical polishing (CMP) to prevent short circuit between different through holes to form tungsten plug, which is convenient for forming metal interconnection (such as aluminum). Among them, in the CMP process, the interlayer dielectric layer (such as silicon oxide) is usually used as the grinding stop layer, so the Ti / TiN layer on the surf...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
CPCH01L21/76804H01L21/76816H01L21/7685
Inventor 张鼎丰闵源
Owner GUANGZHOU CANSEMI TECH INC