Unlock instant, AI-driven research and patent intelligence for your innovation.

Formation method of semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve the problems of large HTH size and inconsistent HTH size, etc.

Active Publication Date: 2021-09-07
SEMICON MFG INT (SHANGHAI) CORP +1
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, when filling metal in the first groove to form the first metal line, the sidewall existing on the inner wall of the first groove will affect the distance (Head to Head, HTH) between the ends of the formed adjacent first metal line, resulting in the formed The HTH size between adjacent first metal lines is relatively large, and the formed HTH size does not meet the expected target

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Formation method of semiconductor device
  • Formation method of semiconductor device
  • Formation method of semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0044] Figure 6 to 26 It is a structural diagram of various steps in the semiconductor device forming process corresponding to a first embodiment of the present invention.

[0045] refer to Image 6 Providing layer to be etched 200, the layer to be etched 200 comprises a plurality of discrete first areas A1 and the second area A2, the first region A1 and second region A2 and white arranged, and adjacent A1 A2 adjacent to the first region and the second region.

[0046] In this embodiment, the plurality of first area A1 and the second area A2 along the first direction X spaced arrangement, wherein the interphase arrangement means: having only one second between the adjacent first region region between adjacent second regions having only a first region.

[0047] In this embodiment, in three first region A1,2 second area A2 as an example. In other embodiments, the number of the first and second regions may choose other values.

[0048] In this embodiment, the region of the first regi...

no. 2 example

[0110] Figure 27 to 38 It is a structural diagram of the steps of a second embodiment of the present invention, in the semiconductor device forming process corresponding.

[0111] The main difference between the first embodiment of the present embodiment is that, in the present embodiment, the first formed in the first region of the first mask layer in the first slot, and then in said second region a first mask layer formed in the second groove.

[0112] In this embodiment, layer to be etched 200, the underlying hard mask layer 220, a first mask layer 210, a material and a method of forming a patterned core layer 300 and spacer material layer 310 are the same as in the first embodiment , not discussed here.

[0113] refer to Figure 27 with Figure 28 , Figure 27 with Figure 9 The overlooking direction, Figure 28 with Figure 10 Cross-sectional view in the same direction, forming a material layer 310 of the sidewall after removing the spacer material layer 310 of the 300 top surface ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a formation method of a semiconductor device, which comprises the steps of providing a to-be-etched layer, wherein the to-be-etched layer comprises a plurality of discrete first regions and second regions, the first regions and the second regions are arranged alternately, and the first regions and the second regions are adjacent to each other; forming a first mask layer on the layer to be etched; forming a patterned core layer on the first mask layer in the first region; forming a side wall material layer on the top and side wall surfaces of the core layer and the surface of the first mask layer; removing the side wall material layer on the top surface of the core layer; removing the core layer and the first mask layer at the bottom of the core layer, and forming a first groove in the first mask layer in the first region; removing the side wall material layer on the surface of the first mask layer in the second region; forming a first pattern layer exposing the first mask layer of the second region; and taking the first pattern layer as a mask, removing the first mask layer in the second region, and forming a second groove in the first mask layer in the second region. According to the formation method provided by the invention, a smaller HHT size can be realized, and the obtained HHT size conforms to an expected target.

Description

Technical field [0001] The present invention relates to the field of semiconductor manufacturing techniques, and more particularly to a method of forming a semiconductor device. Background technique [0002] As the circuit integration increases and the size of the scale, the size of the unit device in the circuit is constantly narrowing, and the requirements for the integrated circuit manufacturing process are constantly increasing, such as the key size continues to decrease, and the chip manufacturing resolution is more and more high. As the design size continues to narrow, the minimum resolution of design graphics has exceeded the limit capability of existing optical lithography platforms, and the industry uses a variety of technical solutions to solve the technical problem, and according to the international semiconductor technology blueprint, Double graphic technology (DPT), extreme UV technology (EUV), electron beam direct write (EBL) and other technical programs have been h...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/033
CPCH01L21/0338H01L21/033H01L21/31144H01L21/0337H01L21/76816H01L21/0335H01L21/0332
Inventor 金吉松
Owner SEMICON MFG INT (SHANGHAI) CORP