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Silicon-germanium substrate structure on multi-layer insulator, and preparation method and application of silicon-germanium substrate structure on multi-layer insulator

Active Publication Date: 2021-10-01
INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003]The existing substrate on the insulating layer is mainly a single layer. In practical applications, the electrostatic characteristics have been improved, but the performance improvement is limited

Method used

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  • Silicon-germanium substrate structure on multi-layer insulator, and preparation method and application of silicon-germanium substrate structure on multi-layer insulator
  • Silicon-germanium substrate structure on multi-layer insulator, and preparation method and application of silicon-germanium substrate structure on multi-layer insulator
  • Silicon-germanium substrate structure on multi-layer insulator, and preparation method and application of silicon-germanium substrate structure on multi-layer insulator

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0059] provide as figure 2 As shown in the SOI substrate, the substrate includes a backing silicon layer 1 , a first insulating layer 2 and a silicon top layer 31 stacked sequentially from bottom to top. The thickness of the first insulating layer 2 is less than 100 nm.

[0060] The silicon top layer 31 is thinned, and the thickness is controlled below 100 nm.

[0061] Then an initial silicon germanium layer 32 is formed on the silicon top layer 31, and the initial silicon germanium layer 32 is Si 1-x Ge x , 0 image 3 structure shown.

[0062] will be like image 3 The structure shown is annealed so that the silicon top layer 31 and the initial silicon germanium layer 32 undergo interlayer diffusion, thereby forming the first silicon germanium layer 3, and the thickness of the obtained first silicon germanium layer 3 is less than 100 nm; then remove the insulating protection Layer 33, obtained as Figure 4 structure shown.

[0063] Then a second insulating layer 4 is f...

Embodiment 2

[0067] provide as figure 2 As shown in the SOI substrate, the substrate includes a backing silicon layer 1 , a first insulating layer 2 and a silicon top layer 31 stacked sequentially from bottom to top. Both the first insulating layer 2 and the silicon top layer 31 are below 100 nm.

[0068] Then an initial silicon germanium layer 32 is formed on the silicon top layer 31, and the initial silicon germanium layer 32 is Si 1-x Ge x , 0 image 3 structure shown.

[0069] will be like image 3 The structure shown is annealed so that the silicon top layer 31 and the initial silicon germanium layer 32 undergo interlayer diffusion, thereby forming the first silicon germanium layer 3, and the thickness of the obtained first silicon germanium layer 3 is less than 100 nm; then remove the insulating protection Layer 33, obtained as Figure 4 structure shown.

[0070] Then, a second insulating layer 4 is formed on the first silicon germanium layer 3, and the thickness of the second ...

Embodiment 3

[0074] provide as figure 2 As shown in the SOI substrate, the substrate includes a backing silicon layer 1 , a first insulating layer 2 and a silicon top layer 31 stacked sequentially from bottom to top. Both the first insulating layer 2 and the silicon top layer 31 are below 100 nm.

[0075] Then an initial silicon germanium layer 32 is formed on the silicon top layer 31, and the initial silicon germanium layer 32 is Si 1-x Ge x , 0 image 3 structure shown.

[0076] will be like image 3 The structure shown is annealed so that the silicon top layer 31 and the initial silicon germanium layer 32 undergo interlayer diffusion, thereby forming the first silicon germanium layer 3, and the thickness of the obtained first silicon germanium layer 3 is less than 100 nm; then remove the insulating protection Layer 33, obtained as Figure 4 structure shown.

[0077] Then, a second insulating layer 4 is formed on the first silicon germanium layer 3, and the thickness of the second ...

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Abstract

The invention relates to a silicon-germanium substrate structure on a multi-layer insulator. The structure comprises a back lining silicon layer, a first insulating layer, a first silicon-germanium layer, n second insulating layers and n second silicon-germanium layers which are sequentially stacked from bottom to top, wherein the n second insulating layers and the n second silicon-germanium layers are alternately and vertically stacked on the first silicon-germanium layer, and the second insulating layers are close to the first silicon-germanium layer; the chemical formula of the silicon germanium material of the first silicon-germanium layer is Si1-yGey; the chemical formula of the silicon germanium material of the second silicon-germanium layer is Si1-zGez, wherein z is greater than 0 and less than or equal to 0.5; the n is a positive integer greater than 1; each second insulating layer is provided with a groove penetrating through the second insulating layer; and the groove is filled with a silicon-germanium material which is the same as the silicon-germanium material of the second silicon-germanium layer. The invention also relates to a preparation method of the silicon-germanium substrate structure on the multi-layer insulator. The substrate structure is beneficial to reducing the short channel effect of the device and improving the on-state current of the device, and is expected to be applied to production of small-size semiconductor devices.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, and in particular relates to a multilayer silicon-germanium-on-insulator substrate structure and a preparation method and application thereof. Background technique [0002] With the continuous development of semiconductor technology, the feature size of semiconductor devices continues to shrink, and the current process technology research and development node has reached 3nm and below. Under the small size, the short channel effect of the device seriously affects the performance of the device. In this case, new materials, new device structures, new integration technologies and packaging technologies are constantly proposed. [0003] Existing substrates on insulating layers are mainly single-layer. In practical applications, the electrostatic properties are improved, but the performance improvement is limited. [0004] Therefore, there is an urgent need to develop a substrate-on-insulat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L21/762
CPCH01L27/1203H01L21/7624H01L27/1218
Inventor 亨利·H·阿达姆松王桂磊罗雪林鸿霄
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI