Manufacturing method for circuit board and circuit board thereof

Abstract

The invention provides a manufacturing method for a circuit board and the circuit board. The method includes steps: providing a substrate having a first metal layer; forming a patterned first opening on the first metal layer to expose the substrate; forming a patterned first dielectric layer on the substrate, the first dielectric layer is made of a photosensitive dielectric material and covers the first opening; photosensitizing the first dielectric layer to cure the first dielectric layer; forming a patterned second metal layer on the first metal layer; forming a patterned third metal layer on the second metal layer, and the third metal layer being adjacent to the first dielectric layer; removing a portion of the first metal layer not covered by the second metal layer; and forming a second dielectric layer on the substrate. A thickness of the third metal layer is greater than a thickness of the second metal layer.

Description

technical field [0001] The invention refers to a method for manufacturing a circuit board and a circuit board made by the method. Background technique [0002] At present, the transmission rate of 4G LTE is about 1Gbps, and the 5G network (frequency 20-150GHz) will use wider channels to communicate with wireless devices, with a bandwidth of up to 800MHz and a transmission rate of about 6-50Gbps. Under such high-speed and high-frequency transmission, there will be high energy consumption and noise interference. Therefore, the design concept of circuit boards used in 5G technology is mainly focused on how to improve impedance matching to reduce loss and noise. In order to achieve such a goal, a three-dimensional circuit technology (3Dtrench Technology) has been proposed, which is to manufacture different copper thicknesses on the same circuit. What Intel Corporation (Intel Corporation) discloses in its patent case US10079158 is exactly such technology. [0003] like Figure ...

AI Technical Summary

Problems solved by technology

This is because the first part 112 and the second part 114 of the signal wire 110 need to go through a second photolithography process (photolithography), but the alignment of the exposure between the second photolithography processes will be different, resulting in the signal wire 110. The second part 114 in is not in the predetermined position

In this way, the effect of reducing loss and noise of the signal wire 110 will be reduced, and unnecessary parasitic capacitance and inductance will be generated.

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