Self-calibration high-precision digital time conversion circuit

Abstract

The invention provides a self-calibration high-precision digital time conversion circuit. The circuit comprises a digital-to-analog converter (DAC), a capacitor array, a switch array composed of a plurality of switches, and an inverter. The digital-to-analog converter DAC is connected with the capacitor array; the capacitor array is connected with the inverter; the inverter is connected with the output end; the digital-to-analog converter DAC, the capacitor array, the inverter and the grounding end are respectively provided with a switch; the capacitor array comprises a fixed capacitance value capacitor cap and a variable capacitance value capacitor cap_vary; the digital-to-analog converter (DAC) charges the capacitor array according to an input digital control word representing time delay, and feeds back the current change of the reference current source to the variable capacitor cap_vary, so as to compensate and calibrate the capacitance value of the capacitor array; and the inverter outputs a clock signal according to the capacitance value of the compensated and calibrated capacitor array. The technical problem that in the prior art, due to the fact that reference current is affected by temperature, technology and voltage changes, offside offset occurs to output clock signals is solved.

Description

technical field [0001] The invention relates to digital time conversion circuit technology, in particular to a self-calibrating high-precision digital time conversion circuit, which belongs to the technical field of digital-analog hybrid integrated circuits. Background technique [0002] In recent years, with the continuous development of technology, phase-locked loop (PLL, Phase Lock Loop) is widely used in communication, AI, Internet of Things, sensors and other applications to generate basic clock signals for RF transceivers, timing control circuits and other circuits middle. It has a crucial impact on the performance of the circuit such as noise. [0003] According to the type of phase-locked loop, it can be divided into analog charge pump phase-locked loop (CPPLL) and all-digital phase-locked loop (ADPLL). Among them, the analog charge pump phase-locked loop has good phase noise performance, but the design complexity and power consumption are higher than the all-digit...

AI Technical Summary

Problems solved by technology

However, for current-mode digital-to-analog conversion circuits, the reference current source in the circuit is affected by changes in temperature, process, and voltage, and the output reference current will change with the

For a high-precision digital time conversion circuit, a small current change will cause an offside shift in its output clock signal

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