Dynamic random access memory and manufacturing method thereof
A technology of dynamic random access and fabrication method, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems such as affecting performance and increasing resistance, and achieve the effect of reducing bit line resistance and improving device performance.
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Embodiment 1
[0076] Figure 6 A schematic diagram of a partial structure of the dynamic random access memory provided in this embodiment, Figure 3A for Figure 6 A simplified layout of the DRAM in , where, Figure 6 for Figure 3A A schematic cross-sectional view of the dynamic random access memory structure in the a-a' direction. Such as Figure 3A as well as Figure 6 As shown, the DRAM provided by this embodiment includes:
[0077] The substrate 100 includes a plurality of active regions 120 and an isolation structure 110 surrounding the plurality of active regions 120;
[0078] The bit line structure 130 is located on the substrate 100 , wherein the bit line structure 130 sequentially includes a metal silicide layer 134 , a conductive layer 132 and a hard mask layer 133 from the substrate 100 upward.
[0079] Specifically, a plurality of active regions (AA) 120 and isolation structures 110 extending along the first direction (D1 direction) are formed in the substrate 100, and t...
Embodiment 2
[0107] This embodiment provides a dynamic random access memory and its manufacturing method, such as Figure 12 As shown, the DRAM provided by this embodiment includes: a substrate 200 including a plurality of active regions 220 and an isolation structure 210 surrounding the plurality of active regions 220; a bit line structure 230 located on the substrate On the bottom 200 , wherein the bit line structure 230 sequentially includes a metal silicide layer 234 , a conductive layer 232 and a hard mask layer 233 upward from the substrate 100 . The difference from Embodiment 1 is that in this embodiment, the metal silicide layer 234 is not in direct contact with the isolation structure 210 .
[0108] Attached below Figure 7 ~ Figure 12 The method for fabricating the DRAM provided by this embodiment will be described in detail.
[0109] see Figure 7 As shown, a substrate 200 is provided, including a plurality of active regions 220 and an isolation structure 210 surrounding the ...
Embodiment 3
[0126] This embodiment provides a dynamic random access memory, such as Figure 13 As shown, the DRAM provided by this embodiment includes: a substrate 300 including a plurality of active regions 320 and an isolation structure 310 surrounding the plurality of active regions 320; a bit line structure 330 located on the substrate On the bottom 300 , wherein the bit line structure 330 sequentially includes a metal silicide layer 334 , a conductive layer 332 and a hard mask layer 333 upward from the substrate 300 .
[0127] In this embodiment, the thickness of the metal silicide layer 334 will be thicker than the thickness of the silicon layer used to react with the metal layer, so that the metal silicide layer 334 is in complete contact with the bottom of the conductive layer 332, that is The metal silicide layer 334 can protrude from the sidewall of the conductive layer 234 , and is not aligned with the sidewall of the conductive layer 332 , with a slightly stepped shape between...
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