Mos device structure

Abstract

The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of Invention[0002]The present invention relates to a semiconductor device and manufacture method thereof. More particularly, the present invention relates to a manufacture method of forming semiconductor device with improved characteristics, and the semiconductor device structure thereof.[0003]2. Description of Related Art[0004]The metal-oxide-semiconductor (MOS) transistor is one of the most important devices widely applied for very-large-scale-integration (VLSI) circuits, including logic circuits, microprocessors and memories. In addition to a gate oxide layer and a conductive gate structure, the MOS transistor further includes a source / drain region having dopants with a conductivity type opposite to that of the substrate.[0005]With the rapid developments of electronic products e.g. telecommunication products, operating speed of transistors is bound to increase. However, due to the limitations in mobility of electrons and holes in silicon,...

AI Technical Summary

Benefits of technology

[0008]The invention provides a method of forming a metal-oxide-semiconductor (MOS) device, which can restrain boron channeling effects and alleviating possible damages caused by ion implantation.

[0009]Accordingly, the present invention provides a semiconductor device with the metal silicide layer higher than the substrate surface, so as to mitigate possible counteracting effects of the metal silicide layer and enhance the device performance.

[0019]For the semiconductor device of the present invention and the manufacture method thereof, because the SiGe layer is covered by the amorphous silicon layer, the upper surface of the source / drain region is higher than the substrate surface and the subsequently formed metal silicide layer thereon is relatively raised. Hence, possible counteracting effect of the tensile stress of the metal silicide toward the compressive stress of the silicon germanium layer is mitigated and the device performance is enhanced.

Problems solved by technology

However, due to the limitations in mobility of electrons and holes in silicon, the applications of the transistors are confined.

However, certain issues still exist in the manufacturing processes involving using SEG process, which may downgrade the device performances.

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