Power on reset circuit capable of generating power on reset signal without fail

A reset circuit and reset signal technology, which is applied in data reset devices, electrical components, electronic switches, etc., can solve the problems that power-on reset signals cannot be generated, internal circuits are not reset, etc.

Inactive Publication Date: 2004-01-21
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is, if the power supply voltage of the existing power-on reset circuit does not rise after being lower than 0.76V, the power-on reset signal cannot be generated
For example, in a DRAM that uses 1.3V as the low power supply voltage in the standby operation mode, there is a problem that the power-on reset signal is not generated after the standby operation mode ends, and the internal circuit is not reset.

Method used

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  • Power on reset circuit capable of generating power on reset signal without fail
  • Power on reset circuit capable of generating power on reset signal without fail
  • Power on reset circuit capable of generating power on reset signal without fail

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0020] FIG. 1 is a circuit diagram showing the overall configuration of a power-on reset circuit according to Embodiment 1 of the present invention. Referring to FIG. 1 , the power-on reset circuit includes CMOS inverter circuits 10 and 12 , a capacitor 14 and an N-channel MOS transistor 18 .

[0021] The CMOS inverter circuit 10 includes a P-channel MOS transistor 102 , an N-channel MOS transistor 104 and a P-channel MOS transistor 106 . P-channel MOS transistor 102 has a gate connected to node NDA, a source connected to power supply node 1 , and a drain connected to node NDB through P-channel MOS transistor 106 . N-channel MOS transistor 104 has a gate connected to node NDA, a drain electrically connected to node NDB, and a source connected to ground node 2 . P-channel MOS transistor 106 is connected between P-channel MOS transistor 102 and node NDB.

[0022] The CMOS inverter circuit 12 includes a P-channel MOS transistor 122 , an N-channel MOS transistor 124 and an N-cha...

Embodiment 2

[0041] In the above-mentioned Embodiment 1, one N-channel MOS transistor 18 is provided, so the voltage value is fixed to the voltage value (1.7 V in Embodiment 1) that activates the power-on reset signal / POR, however, the voltage value It may also be adjusted according to the specifications of the semiconductor integrated circuit device using the power-on reset circuit.

[0042] image 3 It is a diagram showing the configuration of main parts of the power-on reset circuit of the second embodiment for the purpose of adjusting the above-mentioned voltage value. refer to image 3 , in this embodiment 2, instead of the N-channel MOS transistor 18 of the above-mentioned embodiment 1, three N-channel MOS transistors 181 to 181 are connected in series between the source of the N-channel MOS transistor 124 and the ground node 2 183. The respective N-channel MOS transistors 181 to 183 are connected in the form of diodes. Further, fuses 401 to 403 as switching elements are connected...

Embodiment 3

[0046] In the above-mentioned second embodiment, the voltage value of the power-on-reset signal / POR can be adjusted artificially according to the power supply voltage, but the voltage value can also be automatically adjusted according to the power supply voltage VCC.

[0047] 4 is a circuit diagram showing a configuration of main parts of a power-on-reset circuit according to a third embodiment for automatically adjusting a voltage value for activating a power-on-reset signal / POR according to a power supply voltage VCC. Referring to FIG. 4 , in this third embodiment, N-channel MOS transistors 411 to 413 are connected as switching elements instead of the fuses 401 to 403 of the above-mentioned second embodiment. In addition, resistors 431 to 434 are connected in series between the power supply node 1 and the ground node 2, and the connection nodes ND1 to ND3 of the resistors 431 to 434 are connected to the gates of the N-channel MOS transistors 411 to 413, respectively. Inver...

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Abstract

A power on reset circuit includes: interconnected first and second inverter circuits; a capacitor and a buffer circuit. In the power on reset circuit, in order to increase source voltage of an N channel MOS transistor in the second inverter circuit to a voltage higher than ground voltage, a diode-connected transistor is inserted between the source of the transistor and a ground node. Thus, the power on reset circuit never fails to produce the power on reset signal even when power supply voltage is dropped.

Description

technical field [0001] The present invention relates to a power-on reset circuit, and more specifically, to a power-on reset circuit that generates a power-on reset signal for a predetermined period after power is turned on. Background technique [0002] In most semiconductor integrated circuit devices such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and microprocessors, in order to initialize internal circuits that are in an unstable state before power is turned on, a power-on A power-on reset circuit that generates only a power-on reset signal for a specified period afterward. The power-on reset signal is only activated during a specified period before the power supply voltage reaches a specified voltage value, and becomes ineffective when the power supply voltage reaches a specified voltage value. The aforementioned internal circuits are reset in response to the activated power-on reset signal. [0003] On the other hand, recently, se...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/24G06F15/78G11C7/00G11C11/401H03K17/22H03K17/24
CPCH03K17/223G11C11/34
Inventor 丁磊
Owner MITSUBISHI ELECTRIC CORP
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