High-density three-dimensional multilayer memory and preparation method thereof
A three-dimensional multi-layer and memory technology, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems that cannot meet the requirements of mass data storage, large series resistance of memory cells, and affect the performance of memory. The parameters are easy to control, the interlayer resistance is low, and the consistency is good
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Embodiment 1
[0089] Present embodiment is the first embodiment of preparation method, comprises the following steps:
[0090] A1. form the basic structure on the bottom circuit 43: the first conductive medium layer and the insulating medium layer of the predetermined number of layers are set in the mode that the first conductive medium layer 41 and the insulating medium layer 42 overlap each other to form the basic structure, see figure 2 , image 3 ;
[0091] A2. Grooving the basic structure: open a curved dividing groove running from the top layer to the bottom layer on the basic structure, so that the dividing groove divides the basic structure into two staggered and mutually separated interdigitated structures, see Figure 4 , Figure 5 ;
[0092] A3. Substrate-specific deposition is performed on the first conductive medium region located on the inner wall of the division groove, and a buffer zone 71 of a low-doped semiconductor material is formed on the surface region of the first...
Embodiment 2
[0101] Present embodiment is the second embodiment of preparation method, comprises the following steps:
[0102] B1. form the basic structure on the bottom circuit 43: the first conductive medium layer and the insulating medium layer of the predetermined number of layers are set in a manner that the first conductive medium layer 41 and the insulating medium layer 42 overlap each other to form the basic structure, see figure 2 , image 3 ;
[0103] B2. Grooving the basic structure: open a curved dividing groove running from the top layer to the bottom layer on the basic structure, so that the dividing groove divides the basic structure into two staggered and mutually separated interdigitated structures, see Figure 4 , Figure 5 ;
[0104] B3. Substrate-specific deposition is performed on the surface area of the first conductive medium located on the inner wall of the division groove to form a buffer zone 71 of low-doped semiconductor material, see Image 6 , Figure 7...
Embodiment 3
[0111] This embodiment is the third embodiment of the preparation method, comprising the following steps:
[0112] C1. form the basic structure body on the bottom circuit 43: the first conductive medium layer and the insulating medium layer of the predetermined number of layers are set in the mode that the first conductive medium layer 41 and the insulating medium layer 42 overlap each other to form the basic structure body, see figure 2 , image 3 ;
[0113] C2. Grooving the basic structure: open a curved dividing groove running from the top layer to the bottom layer on the basic structure, so that the dividing groove divides the basic structure into two staggered and mutually separated interdigitated structures, see Figure 4 , Figure 5 ;
[0114] C3. Fill the insulating medium in the division groove, and then etch the insulating medium to form a memory cell hole, see Figure 24, Figure 25 ;
[0115] C4. Perform specific deposition on the surface area of the first c...
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