Parallel acceleration extraction method for SPEF parasitic parameters of very-large-scale integrated circuit

Abstract

A parallel acceleration extraction method for SPEF parasitic parameters of a very-large-scale integrated circuit comprises the following steps: starting multiple threads, and dividing a SPEF file into a plurality of data blocks of a basic attribute definition part and a parameter file body part in parallel according to a branch structure of the SPEF file; starting multiple threads, and reading parasitic parameter data required for establishing and analyzing a time sequence diagram of each data block in parallel; and starting multiple threads, and carrying out coupling capacitance combination on each data block in parallel. According to the parallel acceleration extraction method for the SPEF parasitic parameters of the every-large-scale integrated circuit, through fine-grained task division, very objective high parallelism and a good speed-up ratio are achieved, and the response speed of static time sequence analysis in the circuit design optimization process is increased.

Description

technical field [0001] The invention relates to the technical field of Electronic Design Automation (EDA), in particular to an acceleration method for parsing VLSI SPEF files in parallel in static timing analysis. Background technique [0002] At different stages of integrated circuit design, it is necessary to check the timing of the design to ensure that the designed circuit can meet the predetermined timing requirements. Static Timing Analysis (STA) is stimulus-independent and enables fast and accurate measurements of circuit timing to measure circuit performance. [0003] Static timing analysis uses an exhaustive analysis method. It extracts all timing paths in the entire circuit, constructs timing diagrams, calculates the delay propagation of signals on the paths, and finds errors that violate timing constraints. [0004] When calculating the propagation delay of signals, static timing analysis requires many library files, including Liberty, SPEF, SDC, etc. Among the...

AI Technical Summary

Problems solved by technology

Integrated circuit designers extract the SPEF parameters of the current circuit design network through specific parasitic parameter extraction tools, and use these parameters to participate in the calculation and evaluation of power consumption and static timing analysis, and comprehensively evaluate the usability and optimization direction of the current design; in fact, Chip designers need to adjust the circuit design multiple times or perform multiple optimizations to meet the timing and power consumption requirements. During this process, it is necessary to extract the parasitic parameters of the interconnection lines and perform static timing analysis multiple times, which is time-consuming. huge

[0005] In the past few decades, hardware computing units have developed rapidly, and the available computing resources have become more and more abundant, but most of the technologies still stay in single-process (thread) reading, which is far smaller than the available computing resources, resulting in a large number of computing resources. The vacancy and inefficiency of the entire static timing analysis

[0006] At present, the computing resources available for hardware are becoming more and more abundant, but most technologies still stay in single-process (thread) reading, which is far less than the available computing resources, resulting in a large number of vacant computing resources and insufficient efficiency of the entire static timing analysis

There is little research on the direction of computing optimization through multi-process (threading)

Images