A Parallel Accelerated Extraction Method of VLSI SPEF Parasitic Parameters

Abstract

A parallel accelerated extraction method of VLSI SPEF parasitic parameters, comprising the following steps: starting multi-threading, and dividing the file into a plurality of data blocks in parallel in a basic attribute definition part and a parameter file body part according to the branch structure of the SPEF file; Start multi-threading, read in parallel the parasitic parameter data required by each data block to create and analyze the timing diagram; start multi-threading, and combine coupling capacitors for each data block in parallel. The parallel accelerated extraction method of VLSI SPEF parasitic parameters of the present invention, through fine-grained task division, achieves a very objective high parallelism, and a good speed-up ratio, and improves the response of static timing analysis in the process of circuit design optimization speed.

Description

technical field [0001] The invention relates to the technical field of Electronic Design Automation (EDA), in particular to an acceleration method for parsing VLSI SPEF files in parallel in static timing analysis. Background technique [0002] At different stages of integrated circuit design, it is necessary to check the timing of the design to ensure that the designed circuit can meet the predetermined timing requirements. Static Timing Analysis (STA) is stimulus-independent and enables fast and accurate measurements of circuit timing to measure circuit performance. [0003] Static timing analysis uses an exhaustive analysis method. It extracts all timing paths in the entire circuit, constructs timing diagrams, calculates the delay propagation of signals on the paths, and finds errors that violate timing constraints. [0004] When calculating the propagation delay of signals, static timing analysis requires many library files, including Liberty, SPEF, SDC, etc. Among the...

AI Technical Summary

Problems solved by technology

Integrated circuit designers extract the SPEF parameters of the current circuit design network through specific parasitic parameter extraction tools, and use these parameters to participate in the calculation and evaluation of power consumption and static timing analysis, and comprehensively evaluate the usability and optimization direction of the current design; in fact, Chip designers need to adjust the circuit design multiple times or perform multiple optimizations to meet the timing and power consumption requirements. During this process, it is necessary to extract the parasitic parameters of the interconnection lines and perform static timing analysis multiple times, which is time-consuming. huge

[0005] In the past few decades, hardware computing units have developed rapidly, and the available computing resources have become more and more abundant, but most of the technologies still stay in single-process (thread) reading, which is far smaller than the available computing resources, resulting in a large number of computing resources. The vacancy and inefficiency of the entire static timing analysis

[0006] At present, the computing resources available for hardware are becoming more and more abundant, but most technologies still stay in single-process (thread) reading, which is far less than the available computing resources, resulting in a large number of vacant computing resources and insufficient efficiency of the entire static timing analysis

There is little research on the direction of computing optimization through multi-process (threading)

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