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Low quiescent current NMOS type fully-integrated LDO circuit

A quiescent current, fully integrated technology, applied in the direction of adjusting electrical variables, control/regulating systems, instruments, etc., can solve the problems of unexpected circuit restart, increase of LDO quiescent current, large LDO overshoot, etc., to improve PSRR and reduce static electricity. Current, the effect of speeding up recovery

Pending Publication Date: 2021-12-07
SUZHOU UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This will cause the problem of large overshoot of the LDO when the load is switched, especially the undershoot. If it is too large, it may cause an unexpected restart of the circuit.
[0009] In order to improve the load transient response performance, suppress the overshoot voltage at the output terminal and select a reasonable frequency compensation scheme to make the loop stable, the LDO circuit often requires additional complex circuits to control the charge and discharge of the output power tube grid, and these additional circuits are often means more current branches, which inevitably increases the quiescent current of the LDO

Method used

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  • Low quiescent current NMOS type fully-integrated LDO circuit
  • Low quiescent current NMOS type fully-integrated LDO circuit
  • Low quiescent current NMOS type fully-integrated LDO circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0066] see Figure 4 As shown, the present invention provides a low quiescent current NMOS type fully integrated LDO circuit, including an error amplifier circuit, an adaptive bias current source circuit, an NMOS transistor N5 as a power transmission tube, resistors R1 and R2 as load resistors, and a frequency A compensation circuit, an upper overshoot detection circuit and a lower overshoot detection circuit, the upper overshoot detection circuit adaptively controls the opening and closing of the NMOS transistor N6, and the lower overshoot detection circuit adaptively controls the opening and closing of the PMOS transistor P5 ;

[0067] The overshoot detection circuit is configured to turn on the NMOS transistor N6 when detecting the occurrence of the overshoot, so as to provide an additional bias current to the error amplifier circuit, and turn off the NMOS when the output overshoot voltage returns to a value close to the steady state Tube N6;

[0068] The undershoot detec...

Embodiment approach

[0104] The embodiment of the present invention is realized under the 180nm CMOS process, and the goal is to provide the core with a power supply voltage of 1.2V and a maximum load current of 50mA. The operating voltage of the error amplifier circuit may be 2.5-5V, and the power supply voltage of the NMOS transistor N5 may be 1.25-1.6V. The no-load quiescent current of the present invention is only 3.6 μA, realizing the goal of low quiescent current.

[0105] The advantages of the present invention are specifically described below in conjunction with the accompanying drawings

[0106] see Figure 7 As shown, when the load current is switched between 200 μA and 50 mA in 1 ns, the present invention has the effect of obviously accelerating the overshoot recovery speed, and the increase of the lower overshoot recovery speed is particularly obvious.

[0107] see Figure 8 As shown, the undershoot voltage can be restored to within 10% of the final value (ie 1.15V) within 160ns.

...

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PUM

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Abstract

The invention discloses a low quiescent current NMOS (N-channel Metal Oxide Semiconductor) type fully-integrated LDO (Low Dropout Regulator) circuit. The circuit comprises an error amplifier circuit, a self-adaptive bias current source circuit, an NMOS tube N5, resistors R1 and R2, a frequency compensation circuit, an upper overshoot detection circuit and a lower overshoot detection circuit, wherein the upper overshoot detection circuit is used for self-adaptively controlling opening and closing of an NMOS tube N6, the lower overshoot detection circuit is used for self-adaptively controlling opening and closing of a PMOS (P-channel Metal Oxide Semiconductor) tube P5; when the upper overshoot detection circuit detects that upper overshoot occurs, an NMOS (N-channel Metal Oxide Semiconductor) tube N6 is opened so as to provide additional bias current for the error amplifier circuit; when the lower overshoot detection circuit detects that lower overshoot occurs, the PMOS tube P5 is opened, so additional bias current is provided for the error amplifier circuit. According to the circuit, the fast response of the fully-integrated LDO facing dozens of A / mu s load current switching rate can be realized with very low quiescent current.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a low quiescent current NMOS type fully integrated LDO circuit. Background technique [0002] A low-dropout (LDO) linear regulator, generally referred to as LDO for short, is a circuit module that provides a clean and stable voltage source. Fully integrated requires all its components to be implemented on-chip to power modules in a system-on-chip (SoC). SoC often requires multiple fully integrated LDOs to power it, such as one for analog modules, one for RF modules, and another LDO for other modules. The analog module has little interference with the LDO input power supply, and the load current changes relatively slowly; the RF module is easy to interfere with the LDO input power supply, which requires a high power supply rejection ratio (PSRR) in the whole frequency band, and the load current changes rapidly, but the load current change range is not large. ot...

Claims

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Application Information

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IPC IPC(8): G05F1/56
CPCG05F1/56Y02B70/10
Inventor 白春风张开
Owner SUZHOU UNIV
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