Three-dimensional memory and method for preparing three-dimensional memory
A memory and three-dimensional technology, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of increasing the curvature of the substrate of the semiconductor structure, increasing the difficulty of processing other process steps, and high heating temperature of the wafer. Improve performance, reduce cost, and simplify the process
Pending Publication Date: 2021-12-24
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
However, increasing the furnace tube reaction chamber temperature will make the wafer heating temperature too high, and the wafer heating temperature will cause a series of adverse effects, such as significantly increasing the substrate curvature of the semiconductor structure (also known as Bow value), thus increasing the processing difficulty of other subsequent process steps
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[0032] The present application will be described in detail below in conjunction with the accompanying drawings, and the exemplary implementations mentioned herein are only used to explain the present application, and are not intended to limit the scope of the present application.
[0033] The use of cross-hatching and / or shading is generally provided in the figures to clarify boundaries between adjacent elements. Accordingly, neither the presence nor absence of cross-hatching or shading conveys or indicates any assumptions about particular materials, material properties, dimensions, proportions, commonality between illustrated elements, and / or any other characteristics, properties, properties, etc. of the elements. preference or request unless otherwise stated. Furthermore, in the drawings, the size and relative sizes and shapes of elements have been adjusted for clarity and / or descriptive purposes. It should be understood that the drawings are only examples and are not stric...
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Abstract
The invention provides a three-dimensional memory and a method for preparing the three-dimensional memory. The method comprises the steps of forming a stacked structure formed by alternately stacking insulating layers and sacrificial layers on a substrate; forming a channel hole penetrating through the stacked structure, wherein the channel hole extends into the substrate to form a bottom groove, and a defect layer exists on the inner surface of the bottom groove; irradiating the inner surface of the bottom groove by using laser under the atmosphere of reducing gas so as to enable the defect layer in the bottom groove to be melted and recrystallized; and performing epitaxial growth on the recrystallized layer within the bottom channel to form an epitaxial layer. According to the preparation method, the increase of the key size of the channel hole caused by removing the oxide layer and the defect layer in the traditional process can be avoided; and the laser only acts on an atomic layer with the limited depth, and the substrate is not obviously bent due to heat generated by the laser, so that the contribution of a reducing gas high-temperature annealing process to the curvature of the substrate is reduced. In addition, the process can be simplified, and the cost is remarkably reduced.
Description
technical field [0001] The present application relates to the field of semiconductors, and more specifically, to a method for manufacturing a three-dimensional memory, especially an epitaxial growth process in the method for manufacturing a three-dimensional memory. Background technique [0002] Single crystal epitaxial growth is widely used in the manufacturing process of semiconductor products, such as 3D NAND, DRAM, Flash, etc. The cleanliness of the surface of the single crystal substrate is a key factor determining the quality of the epitaxial layer (eg, number of surface defects, growth uniformity in repeating units, etc.). Taking 3D NAND three-dimensional memory as an example, in the channel hole etching process for forming channel holes, serious defects are usually caused to the substrate, and the surface of the bottom trench formed in the substrate will also contain defects of a certain thickness Layers (which include fractal and / or amorphous), polymers containing ...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L27/11524H01L27/11556H01L27/1157H01L27/11582H01L21/268
CPCH01L21/268H10B41/35H10B41/27H10B43/35H10B43/27
Inventor 颜元张豪
Owner YANGTZE MEMORY TECH CO LTD