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Semiconductor package and forming method thereof

A packaging and semiconductor technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as inability to closely adhere chips and tapes, product deformation, and inability to directly form RDLs

Pending Publication Date: 2021-12-28
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] The chip first fan-out (fan out) process based on the lead frame (Lead frame), usually when the active surface of the chip faces down the direct copper interconnection (Direct Cu Interconnection, DCI) production, it is necessary to The tape bonded with the chip is bonded to the tape. After the dielectric layer is filled, the tape is removed and the redistribution layer (RDL) circuit is directly made on the active surface of the chip. However, the general pressure bonding method cannot make the chip and The adhesive tape is tightly attached, so it is easy to cause subsequent process resin (resin) or epoxy molding compound (Epoxy Molding Compound, EMC) to seep into the gap between the adhesive tape and the chip and cover the pad of the chip, resulting in failure of subsequent RDL. formed directly on the pad
If the above problems are improved by using a strong adhesive tape, there will often be technical problems in removing the tape, such as product deformation, product residue, etc.

Method used

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  • Semiconductor package and forming method thereof
  • Semiconductor package and forming method thereof
  • Semiconductor package and forming method thereof

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Embodiment Construction

[0030] In order to better understand the spirit of the embodiments of the present application, it will be further described below in conjunction with some preferred embodiments of the present application.

[0031] Embodiments of the present application will be described in detail below. Throughout the specification of the present application, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the accompanying drawings are illustrative, diagrammatic and are used to provide a basic understanding of the application. The examples of the present application should not be construed as limiting the present application.

[0032] As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and account for minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances in whi...

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Abstract

The embodiment of the invention provides a semiconductor package. The semiconductor package comprises: a lead frame; a chip located in the lead frame; a dielectric layer covering the lead frame and the chip; and a rewiring layer located on the active surface of the chip and the dielectric layer, wherein the rewiring layer is in contact with the active surface of the chip, the rewiring layer is provided with a first step structure extending on the dielectric layer and the active surface, and the part, located on the dielectric layer, of the rewiring layer is lower than the active surface of the chip. The object of the invention is to provide the semiconductor package and a forming method thereof to optimize performance of the semiconductor package.

Description

technical field [0001] Embodiments of the present application relate to semiconductor packages and methods of forming the same. Background technique [0002] The chip first fan-out (fan out) process based on the lead frame (Lead frame), usually when the active surface of the chip faces down the direct copper interconnection (Direct Cu Interconnection, DCI) production, it is necessary to The tape bonded with the chip is bonded to the tape. After the dielectric layer is filled, the tape is removed and the redistribution layer (RDL) circuit is directly made on the active surface of the chip. However, the general pressure bonding method cannot make the chip and The adhesive tape is tightly attached, so it is easy to cause subsequent process resin (resin) or epoxy molding compound (Epoxy Molding Compound, EMC) to seep into the gap between the adhesive tape and the chip and cover the pad of the chip, resulting in failure of subsequent RDL. formed directly on the pad. If the abov...

Claims

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Application Information

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IPC IPC(8): H01L23/495H01L23/498H01L23/31H01L21/56H01L21/683
CPCH01L23/4952H01L23/49541H01L23/49838H01L23/3107H01L21/56H01L21/6836H01L2224/24
Inventor 施佑霖李志成
Owner ADVANCED SEMICON ENG INC