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Semiconductor structure and forming method thereof

A semiconductor and isolation layer technology, applied in the field of semiconductor structure and its formation, can solve problems such as performance needs to be improved, and achieve the effect of improving formation efficiency, improving efficiency, and improving performance

Pending Publication Date: 2022-01-07
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, compared with the device structure of GAA, the electrical performance of the forksheet structure MOSFET in the prior art still needs to be improved because the forksheet structure is not a fully enclosed structure.

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

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Embodiment Construction

[0045] As in the context of the background, the electrical properties of the GAA structure MOSFET remain to be improved in the prior art. Specifically, the accompanying drawings will be specifically described below.

[0046] Please refer to figure 1 and figure 2 , figure 2 Yes figure 1 In the cross section of the AA line, a substrate 100 is provided; a fin structure 101 arranged in parallel along the first direction X is formed on the substrate 100, and the adjacent fin structure 101 has an isolation trench. (Not indicated), the fin structure 101 includes a sacrificial layer 103 overlapping along the surface of the substrate 100, and a channel layer 104 located between adjacent two-layer sacrificial layer 103; An isolation layer 102 is formed in the isolation trench that fills the isolation trench.

[0047] Please refer to image 3 and Figure 4 , Figure 4 Yes image 3 In the cross section of the BB line, a plurality of dummy gate layers 105 flowing across the neighboring fin structu...

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Abstract

The invention discloses a semiconductor structure and a forming method thereof. The structure comprises a substrate; a plurality of fin structures which are located on the substrate, wherein an isolation structure and an isolation groove formed in the isolation structure are arranged between every two adjacent fin structures, and each fin structure comprises a plurality of channel layers in the normal direction of the surface of the substrate; gate structures which are located on the substrate and stretch across the adjacent fin structures, wherein the gate structures surround the channel layer; a dielectric layer which is positioned on the substrate; a second isolation layer which is located in the isolation groove, wherein the gate structures cover part of the side wall and the top surface of the second isolation layer, and a gap is formed between the second isolation layer and the adjacent fin structure. The gate structures cover part of the side wall and the top surface of the second isolation layer through the second isolation layer located in the isolation groove, and the gap is formed between the second isolation layer and the adjacent fin structure. Therefore, the gate structure can surround the channel layer all around, so that the area of a channel region formed by surrounding the channel layer by the gate structure is increased, and the performance of the final semiconductor structure is effectively improved.

Description

Technical field [0001] The present invention relates to the field of semiconductor manufacturing techniques, and more particularly to a semiconductor structure and a method of forming thereof. Background technique [0002] Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is one of the most important components in modern integrated circuits, and the basic structure of MOSFET includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure including : The gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer on the surface of the gate dielectric layer; the source leak-doped region located in the semiconductor substrate of the gate structure. [0003] With the development of semiconductor technology, traditional planar MOSFETs have weakened the control capability of channel currents, causing severe leakage current. Fin Field Effect Transistor (FIN FET) is an emer...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/423
CPCH01L29/66803H01L29/66545H01L29/785H01L29/42356
Inventor 金吉松
Owner SEMICON MFG INT (SHANGHAI) CORP
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