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Forming method of semiconductor structure

A technology of semiconductor and dummy gate structure, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, and nanotechnology for information processing, etc. Effects of film etching, improvement of formation efficiency, and improvement of performance

Pending Publication Date: 2021-10-26
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the electrical performance of the GAA structure MOSFET in the prior art still needs to be improved

Method used

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  • Forming method of semiconductor structure

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Embodiment Construction

[0039] As mentioned in the background art, the electrical performance of the GAA structure MOSFET in the prior art still needs to be improved. The following will describe in detail in conjunction with the accompanying drawings.

[0040] Please refer to figure 1 , providing a substrate 100; forming a plurality of fin structures 101 arranged in parallel along a first direction on the substrate 100, with isolation trenches (not marked) between adjacent fin structures 101, the The fin structure 101 includes several layers of sacrificial layers 103 overlapping along the normal direction of the surface of the substrate 100, and a channel layer 104 located between two adjacent layers of the sacrificial layers 103; formed on the substrate 100 Across the dummy gate structures 105 adjacent to the fin structures 101 , the dummy gate structures 105 extend along a second direction, and the first direction is perpendicular to the second direction.

[0041] Please refer to figure 2 , rem...

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Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; forming a plurality of fin structures on the substrate, wherein an isolation groove is formed between the adjacent fin structures; forming a first isolation layer in the isolation groove; forming a second isolation layer filling the isolation groove on the surface of the first isolation layer; and removing the first isolation layer. According to the technical scheme of the invention, the first isolation layer is removed, so that the gaps are formed between the second isolation layer and the adjacent fin structures, and the sacrificial layer can be removed from the two side walls of the sacrificial layer at the same time, thereby effectively improving the etching removal efficiency. In the formation process of the gate structure, deposition formation can be carried out from the two sides of the gate groove at the same time, and the formation efficiency of the gate structure is effectively improved. Besides, the second isolation layer is formed firstly, so that subsequent cutting of the dummy gate structure is avoided, the step of mask etching of a photomask is omitted, and the process difficulty is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] Metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the most important elements in the modern integrated circuit, and the basic structure of MOSFET comprises: semiconductor substrate; Be positioned at the gate structure of semiconductor substrate surface, described gate structure comprises : a gate dielectric layer on the surface of the semiconductor substrate and a gate electrode layer on the surface of the gate dielectric layer; source and drain doped regions in the semiconductor substrate on both sides of the gate structure. [0003] With the development of semiconductor technology, the traditional planar MOSFET's ability to control the channel current becomes weaker, resulting in serious leakage current. Fin Field Effect Transistor (Fin FET) is an emerging multi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78H01L29/423
CPCH01L29/42356H01L29/785H01L29/66803H01L21/823481H01L21/823437H01L29/66439H01L29/775H01L29/0673B82Y10/00H01L29/78696H01L29/42392H01L21/823431H01L21/823412H01L29/6681
Inventor 王楠
Owner SEMICON MFG INT (SHANGHAI) CORP
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