A read-write test method for memory chip flash by bypassing a customized system-on-chip chip
A technology for reading and writing testing and storing chips, which is applied in static memory, instruments, etc., can solve problems such as maintenance cycle, unsatisfactory cost and quality, difficult board card, fault location, etc., to shorten the maintenance cycle, improve test efficiency, low cost effect
Pending Publication Date: 2022-01-25
广州航新电子有限公司
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Problems solved by technology
[0005] The present invention provides a test method for reading and writing memory chip flash by bypassing the customized system-on-chip chip, which solves the difficulty in testing the current board card maintenance, and it is difficult to test the board card in all directions to quickly locate the fault. Problems leading to unsatisfactory maintenance intervals, costs and quality
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[0037] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.
[0038] Please refer to figure 1 , figure 2 and image 3 ,in figure 1 A flow chart of calculating the JTAG interface characteristic parameters of a test method that bypasses the custom SoC chip to read and write the memory chip flash provided by the present invention, figure 2 for figure 1 The overall flow chart of the test method for flash reading and writing of the memory chip bypassing the custom SoC chip as shown, image 3 for figure 1 Shown is a schematic diagram of the hardware wiring of the test method for reading and writing the memory chip flash by bypassing the custom SoC chip. A test method for reading and writing memory chip flash by bypassing a customized system-on-chip chip, comprising the following steps:
[0039] S1. First, send multiple sets of specific binary sequence codes to the data line TDI of the JTAG port through the parall...
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The invention provides a read-write test method for memory chip flash by bypassing a customized system-on-chip chip. Comprising the following steps: sending multiple groups of specific binary sequence codes to a data line TDI of a JTAG port through a parallel port of a computer; with the help of an oscilloscope, calculating the instruction length, the data length and the highest transmission speed of the JTAG interface through code streams observed on a data line TDO of the JTAG interface; then, converting an operation instruction corresponding to the specification and model of the flash chip needing to be subjected to read-write test into a corresponding binary sequence code according to characteristic parameters of a JTAG interface, and finally loading the binary sequence code to a parallel port card of a computer, so that the parallel port card can automatically match the level of the JTAG interface and shift the sequence code into the pin of the system-on-chip according to the sequence; meanwhile, isolating the internal control logic circuit of the system-on-chip automatically; finally, sending the binary sequence code accurately to the control bus of the flash chip, and realizing the full-automatic read-write test of the flash storage chip.
Description
technical field [0001] The invention relates to the field of reading and writing testing, in particular to a testing method for reading and writing flash of a memory chip by bypassing a customized system-on-chip chip. Background technique [0002] With the development of semiconductor process technology, especially the maturity of ultra-deep submicron process technology, it is possible to integrate different functional modules, memory, and peripheral circuits on a silicon chip. This complete system that integrates various functional modules on one chip is the system-on-chip (SOC). System-on-a-chip has the characteristics of light weight, small size, low power consumption, and fast operation speed. Therefore, as the functions of current civil aviation aircraft become more and more powerful, the required avionics systems are becoming more and more complex. However, due to factors such as fuel economy and other factors, the overall aircraft The weight needs to be strictly co...
Claims
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Login to View More IPC IPC(8): G11C29/36G11C29/38G11C29/56
CPCG11C29/36G11C29/38G11C29/56
Inventor 方文栋刘会军曾琦波饶金桥
Owner 广州航新电子有限公司