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Method for manufacturing DRAM (Dynamic Random Access Memory) capacitor

A capacitor and electrode technology, applied in the field of semiconductor memory devices, can solve the problems of increasing production time and production cost, and achieve the effect of reducing process cost and production time

Pending Publication Date: 2022-02-18
INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The existing method is to support the capacitor. However, the formation of the support layer usually uses the ArF immersion exposure (ArFImmersion Photo) process, but this process leads to increased production costs and increased production time.

Method used

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  • Method for manufacturing DRAM (Dynamic Random Access Memory) capacitor
  • Method for manufacturing DRAM (Dynamic Random Access Memory) capacitor
  • Method for manufacturing DRAM (Dynamic Random Access Memory) capacitor

Examples

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Embodiment Construction

[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0027] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, s...

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Abstract

The invention relates to a method for manufacturing a DRAM (Dynamic Random Access Memory) capacitor, which comprises the following steps of: sequentially forming a barrier layer, a first molding layer, a first isolating layer, a second molding layer, a second isolating layer and a sacrificial layer on a semiconductor substrate, and then penetrating to form a plurality of slotted holes; forming cylindrical lower electrodes in all the slotted holes; forming a side wall on the outer side of the cylindrical lower electrode; and etching the second isolating layer, the second molding layer, the first isolating layer and the first molding layer based on the side walls, wherein the left isolating layer forms a support body of the lower electrode. The side wall is used as a mask, and other molding layers and isolation layers are etched and removed, so that the support body can be simply formed, the process cost is reduced, and the production time is shortened. Even if the capacitor has a very high height-width ratio, the capacitor does not topple over, and the problem that the capacitor topples over can be fundamentally solved.

Description

technical field [0001] The present application relates to a semiconductor memory device, in particular to a method for manufacturing a DRAM capacitor. Background technique [0002] As semiconductor devices become more highly integrated, the horizontal area of ​​a unit cell on a semiconductor substrate will gradually decrease. Even though the horizontal area of ​​a unit cell on a semiconductor substrate is gradually reduced, in order to store charges in a semiconductor device, a sufficiently high capacitance of a capacitor needs to be maintained. But in order to maintain the capacitance of the capacitor, the height of the bottom electrode needs to be increased to enlarge the contact area between the bottom electrode and the dielectric layer. However, increasing the height of the bottom electrode will cause the bottom electrode to collapse because the aspect ratio (Aspect Ratio) of the bottom electrode is too high. In addition, the aspect ratio of the lower electrodes may ca...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8242H01L27/108H10B12/00
CPCH10B12/03
Inventor 许民张铉瑀吴容哲姜东勋杨涛李俊峰王文武
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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