Anti-static protection structure and high-voltage integrated circuit

Abstract

The invention discloses an anti-static protection structure. The anti-static protection structure comprises an N well and a P well which are formed in a substrate, the upper parts and the middle parts of the N well and the P well are separated by STI, and the lower parts are adjacent; sTI is attached to the upper portion of the N well, P-type heavy doping is injected, and an N well P heavy doping area is formed; n-type heavy doping is injected at the upper part of the N well far away from the STI to form an N-well N heavily doped region; sTI is attached to the upper portion of the P well, P-type heavy doping is injected, and a P well P heavy doping area is formed; the N-well P heavily doped region and the N-well N heavily doped region are short-circuited to form an anode of the anti-static protection structure; and the P heavily doped region of the P well is used as a cathode of the anti-static protection structure. According to the anti-static protection structure, no hysteresis effect can be achieved, high trigger voltage and maintaining voltage can be easily obtained, high secondary breakdown current is achieved, and when the anti-static protection structure is applied to high-voltage port anti-static protection design, the series connection number needed by multi-stage series connection and the layout area of a single-stage protection unit can be saved. The invention also discloses a high-voltage integrated circuit.

Description

technical field [0001] The invention relates to a semiconductor circuit structure, in particular to an antistatic protection structure and a high-voltage integrated circuit. Background technique [0002] The anti-static protection design of high-voltage circuits has always been a technical problem, because the core of high-voltage circuits: high-voltage devices (for example, LDMOS (Laterally Diffused Metal Oxide Semiconductor)) are not suitable for ordinary low-voltage devices. For anti-static protection design, because the characteristics shown by the hysteresis effect curve of high-voltage devices are very poor. Depend on figure 1 The hysteresis effect curve of the conventional high-voltage device LDMOS can be drawn as follows: 1) The holding voltage (Vh) is too low, often much lower than the operating voltage of the high-voltage circuit, and it is easy to cause the latch-up effect when the high-voltage circuit works normally; 2) The secondary The breakdown current (ther...

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Problems solved by technology

[0005] However, the disadvantage of low-voltage PMOS devices is that the secondary breakdown current (It2) of the hysteresis effect is relatively small, and the trigger voltage Vt1 of low-voltage PMOS devices is mainly determined by its drain breakdown voltage (Bvdss). Therefore, when multi-stage series is used for high-voltage anti-static protection design, more series stages are required. For example, taking a 32V high-voltage process platform as an example, the trigger voltage Vt1 and maintenance voltage Vh of the low-voltage PMOS device of the high-voltage process platform About 10.5V, specifically as image 3 As shown, it is often necessary to connect 4 levels of low-voltage PMOS devices in series to achieve anti-static protection for 32V high-voltage ports.

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