Fan-out wafer level packaging structure and packaging method

Abstract

The invention provides a fan-out type wafer level packaging structure and a preparation method, the structure comprises more than two semiconductor chips with welding pads, the semiconductor chips are arranged in a fan-out type wafer array, and each semiconductor chip has a respective initial position; the plastic packaging layer covers the surfaces of the semiconductor chips and among the semiconductor chips, each semiconductor chip has a respective offset position after plastic packaging, and the offset position has an offset distance relative to the initial position; the rewiring layer is formed on the semiconductor chips so as to realize interconnection among the semiconductor chips, the rewiring layer at least comprises a first rewiring layer, and the first rewiring layer is formed on the surfaces of the semiconductor chips and is aligned and connected with welding pads of the semiconductor chips; and a metal bump formed on the rewiring layer. According to the fan-out wafer level packaging structure, effective alignment of the semiconductor chip and the rewiring layer can be realized, and the yield of wafer packaging is improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, and in particular relates to a fan-out wafer-level packaging structure and a packaging method. Background technique [0002] With the rapid development of the integrated circuit manufacturing industry, people's requirements for the packaging technology of integrated circuits are also increasing. The existing packaging technologies include ball grid array packaging (BGA), chip size packaging (CSP), wafer level packaging (WLP) ), three-dimensional packaging (3D) and system in package (SiP), etc. Among them, wafer-level packaging (WLP) is gradually adopted by most semiconductor manufacturers due to its outstanding advantages. All or most of its process steps are completed on silicon wafers that have completed the previous process, and finally the wafer Direct dicing into separate individual devices. Wafer-level packaging (WLP) has its unique advantages: ① high packaging processing ...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a fan-out wafer level packaging structure and packaging method, which is used to solve the problem of the fan-out wafer level packaging in the prior art after the semiconductor chip is plastic-encapsulated. Warping of the wafer and drift of the semiconductor chip increase the difficulty of the subsequent packaging process, thus affecting the yield of the wafer packaging, etc.

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