A filter chip wafer-level packaging structure and packaging process

Abstract

The invention provides a filter chip wafer-level packaging structure and packaging technology. The filter chip wafer-level packaging structure includes a filter chip wafer and a silicon lid wafer; both the filter chip wafer and the silicon lid wafer are provided with a multi-layer metal superimposed metal bonding layer; the The filter chip wafer and the silicon cap wafer are bonded and connected through the multi-layer metal stacked metal bonding layer to form a filter cavity. Wherein, the thickness of the filter cavity is not less than 2 μm. The encapsulation structure and encapsulation process can effectively reduce the process cost and improve the mechanical strength of the silicon cap wafer.

Description

technical field [0001] The invention provides a filter chip wafer-level packaging structure and packaging process, which belong to the technical field of thin film filters. Background technique [0002] Wafer-level packaging of filter chips is an indispensable link in the manufacturing process of thin-film filters. In the existing packaging structure, the electrode lead metal substrate on the filter wafer is usually composed of two layers of metal bonding layer and metal bonding layer. Metal film structure. Moreover, the groove structure is formed on the silicon cap wafer by etching to form the filter cavity, which has the following two defects: [0003] First: it is necessary to introduce an additional photolithography etching process level to form a groove cavity structure on the silicon cap 200, which is an additional process cost. [0004] Second: 200 times of etching on the silicon cap wafer into a dense groove structure, forming many convex and concave structures, re...

AI Technical Summary

Problems solved by technology

[0005] The invention provides a filter chip wafer-level packaging structure and packaging process, which are used to solve the problems in the prior art that the process cost is too high, the mechanical strength of the silicon cap wafer is insufficient, and the structural strength of the packaged chip is insufficient, and the thickness cannot be reduced. , the technical solution adopted is as follows:

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