Semiconductor structure and preparation method thereof, three-dimensional memory and storage device

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a three-dimensional memory and a storage device, relates to the technical field of semiconductor chips, and aims to solve the problem of low integration level of a peripheral circuit of the three-dimensional memory. The semiconductor structure can be divided into a high-voltage well region and a low-voltage well region; the semiconductor structure comprises a substrate which comprises a first groove and at least one second groove, the first groove is located in a high-voltage well region, and the second groove is located in a low-voltage well region; the first isolation structure is arranged in the first groove; the thickness of the first isolation structure is greater than the depth of the first groove; the second isolation structure is arranged in the second groove; the thickness of the second isolation structure is smaller than the depth of the second groove; the first gate oxide layer is located in the high-voltage well region; the first gate oxide layer is disposed on the surface of the substrate and exposes the first isolation structure. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductor chips, and in particular to a semiconductor structure and a manufacturing method thereof, a three-dimensional memory and a storage device. Background technique [0002] As the feature size of the memory cell approaches the lower limit of the process, the planar process and manufacturing technology becomes challenging and expensive, which causes the storage density of 2D or planar NAND flash memory to approach the upper limit. In order to overcome the limitations brought by 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases storage density by three-dimensionally arranging memory cells on a substrate. [0003] In the three-dimensional memory, peripheral circuits are used to perform logic operations, and to control and detect the switch states of each memory cell string to realize data storage and reading. ...

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Problems solved by technology

[0005] Embodiments of the present disclosure provide a semiconductor structure and its preparation method, a three-dimensional memory and a storage device, aiming to solve the problem of low integration of peripheral circuits of the three-dimensional memory

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