Three-dimensional integrated embedded micro-channel active heat dissipation packaging method and structure
A technology of active heat dissipation and three-dimensional integration, which is applied in semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problem of low heat dissipation efficiency of three-dimensional packaging, achieve three-dimensional heterogeneous integration, reduce thermal resistance, and improve heat dissipation efficiency effect
Pending Publication Date: 2022-05-03
58TH RES INST OF CETC
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[0004] The purpose of the present invention is to provide a three-dimensional integrated embedded micro-channel active heat dissipation packaging method and structure to solve the problem of low heat dissipation efficiency of the existing three-dimensional packaging
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[0041] A three-dimensional integrated embedded micro-channel active heat dissipation packaging method and structure proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.
[0042] The invention provides a three-dimensional integrated embedded micro-channel active heat dissipation packaging method, the process of which is as follows figure 1 shown, including the following steps:
[0043] Step S11, providing the substrate 111, etching it to fill holes to form TSV copper pillars 112, and thinning it so that it leaks out to make a silicon-based substrate, such as fi...
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Abstract
The invention discloses a three-dimensional integrated embedded micro-channel active heat dissipation packaging method and structure, and belongs to the field of integrated circuit packaging. Carrying out etching and hole filling on the substrate to form a TSV copper column, and thinning the TSV copper column to prepare a silicon-based substrate; etching a micro-channel groove and an inlet and outlet channel blind hole on the silicon-based substrate; carrying out silicon-silicon bonding on the micro-channel cover plate and the silicon-based substrate; welding the TSV switching chip on the silicon-based substrate in a flip-chip manner, and bonding the heterogeneous chip with the micro-channel cover plate; filling gaps among the bumps at the flip-chip bonding position of the TSV switching chip with underfill; the inverted TSV switching chip and the heterogeneous chip are subjected to potting, curing and reconstruction to form a resin wafer; thinning the copper columns exposed out of the TSV switching chip and the salient points exposed out of the heterogeneous chip; forming a plurality of layers of interconnected rewiring on the resin wafer; the silicon-based substrate is thinned; a heterogeneous chip is fixed in a chip slot, and RDL and UBM multilayer interconnection metal rewiring is realized in sequence; and planting a solder ball at the UBM, and scribing the three-dimensional integrated silicon-based wafer to form a final packaging body.
Description
technical field [0001] The invention relates to the technical field of integrated circuit packaging, in particular to a three-dimensional integrated embedded micro-channel active heat dissipation packaging method and structure. Background technique [0002] With the development of microelectronics and micro-electromechanical systems (MEMS) technology, especially the emergence of new interconnection technologies such as flip-chip (FC) and multi-chip modules (MCM), chip integration and performance have been continuously improved. The rapid development of chip miniaturization and high integration has brought great challenges to the effective heat dissipation of electronic chips. Especially in the three-dimensional packaging system, more and more attention has been paid to the thermal management of the package. This is because: (1) multiple chips are often integrated in the three-dimensional packaging system, which generates a lot of heat, but the packaging area does not increas...
Claims
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IPC IPC(8): H01L23/473H01L23/48H01L25/065H01L21/56H01L21/48
CPCH01L23/473H01L21/4882H01L21/563H01L23/481H01L25/0652H01L2224/18
Inventor 周超杰夏晨辉王刚明雪飞王成迁
Owner 58TH RES INST OF CETC