Register architecture of RISC architecture processor, register block and RISC architecture processor

Abstract

The invention discloses a register architecture of an RISC architecture processor, a register block and the RISC architecture processor, and relates to the technical field of processors. The register architecture comprises a plurality of general registers and a plurality of special registers; wherein the general register is used for being provided for a processor to execute general read-write operation on the general register according to an instruction of the general register; and the special register is used for enabling a processor to execute condition judgment, jump type operation or operation type operation on the special register according to a specified instruction. Therefore, the types of processor instruction set condition judgment/jump type instructions can be reduced, the types and the number of instructions specially used for processing zone bits and calculation results exceeding bit width are reduced, the implementation difficulty and the cost of processor hardware design are reduced, the performance of the processor for executing condition judgment, jump type operation or operation type operation is improved, and the method and the device are suitable for popularization and application. And the instruction overhead of the operation is reduced, and the performance of the processor is not obviously reduced.

Description

technical field [0001] The present invention relates to the technical field of processors, in particular to a register architecture, a register group and a RISC architecture processor of a RISC architecture processor. Background technique [0002] With the development of integrated circuit technology, the scale of the processor is getting bigger and bigger, the structure is getting more and more complex, and the performance is getting higher and higher. [0003] The current processors are roughly divided into two types of architectures according to the technical characteristics of the instruction set: complex instruction set processors (Complex Instruction Set Computing, CISC) and reduced instruction set processors (Reduced Instruction Set Computing, RISC). The instruction set system of the RISC architecture is relatively simple, only a limited number of commonly used and relatively simple instructions need to be implemented, and other complex operations are completed by a c...

AI Technical Summary

Problems solved by technology

[0006] The embodiment of the present invention aims to provide a register architecture of a RISC architecture processor, a register set, and a RISC architecture processor, aiming at solving the complexity and / or the operation of flag bits on the results of instructions executed by existing processors Calculation results that exceed the bit width of a single register may cause processor performance degradation, resulting in increased hardware design circuit complexity and software programming complexity.

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