Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is provided with a discrete fin part lamination structure; forming a gate structure crossing the fin laminated structure on the substrate; etching the fin part laminated structure by taking the gate structure as a mask to form a second fin part and a second sacrificial layer; etching the first fin part layer and the first sacrificial material layer to form a first fin part and a first sacrificial layer; forming a first source-drain doping layer on the substrate at two sides of the first fin part and the first sacrificial layer; forming a first dielectric layer on the first source-drain doped layer; a second source-drain doping layer is formed on the first dielectric layer; and removing the first sacrificial layer, the second sacrificial layer and the gate structure. According to the scheme, the vertically stacked complementary field effect transistor can be formed, and the performance of the formed semiconductor device is improved.

Description

technical field [0001] The present invention relates to the field of semiconductor integrated circuits, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] During the manufacture of semiconductor devices, various manufacturing processes such as film deposition processes, etching mask creation processes, patterning processes, photoresist development processes, material etching and removal processes, and doping processes are performed. These processes are repeatedly performed to form desired semiconductor device elements on the semiconductor substrate. Historically, transistors have been formed using microfabrication in a plane with wiring / metal formed thereon, and thus transistors have been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, but are becoming more challenging as scaling moves into single-digi...

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Problems solved by technology

[0004] However, forming vertically stacked complementary field-effect transistors presents unique challenges

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