Successive approximation analog-to-digital converter

Abstract

The invention discloses a successive approximation type analog-to-digital converter which comprises a fine analog-to-digital conversion unit, a rough analog-to-digital conversion unit, a voltage-time converter, a single-end time generator, a first time-to-digital converter, a second time-to-digital converter, a summator and a data combinational logic structure. The rough analog-to-digital conversion unit and the fine analog-to-digital conversion unit are connected through a detection skipping logic structure; the fine analog-to-digital conversion unit is electrically connected with the voltage-time converter, the single-end time generator and the first time-to-digital converter in sequence; the second time-to-digital converter is electrically connected with the first time-to-digital converter through the time margin generator; the summator is electrically connected with the first time-to-digital converter and the second time-to-digital converter; and the data combinational logic structure is electrically connected with the fine analog-to-digital conversion unit, the rough analog-to-digital conversion unit, the single-end time generator and the summator. According to the successive approximation type analog-to-digital converter, the conversion speed is high, and good PVT robustness is achieved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a successive approximation analog-to-digital converter. Background technique [0002] The successive approximation register analog-to-digital converter is energy efficient in the medium resolution and speed range, mainly due to its single comparator architecture and dynamic power characteristics. However, since the comparator has stricter noise requirements for a few least significant bits, its power-saving efficiency drops significantly with increasing resolution. Two-step SAR ADCs provide a power-efficient alternative to high-resolution SAR ADCs by eliminating those critical comparisons with one-shot low-noise amplification. However, at low power supply, the voltage domain headroom value in two-step SAR ADCs faces the challenge of limited available space. [0003] In the case of low power consumption, a hybrid voltage-domain and time-domain architecture is a promi...

AI Technical Summary

Problems solved by technology

The second challenge is the slow conversion speed of SARADC assisted by traditional TDC, which is not only due to the slow conversion speed of VTC at small headroom voltage, but also due to the smaller power supply, TDC has a larger LSB step size

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