Bypass switch bias voltage generating circuit
A technology of bias voltage and circuit generation, applied in the direction of adjusting electrical variables, control/regulating systems, instruments, etc., can solve problems such as unpredictability, wrong working state, abnormal switching state of FET transistors, etc.
Active Publication Date: 2022-07-08
苏州悉芯射频微电子有限公司
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) with the help of the power supply voltage VDD, and Vbias changes with the change of VDD, so Vctrl-Vbias also changes with the change of VDD, and its value may appear unpredictable, resulting in abnormal switching status of the FET transistor
When Vctrl is a logic low level (take 0V as an example), the first enhanced FET is turned off, Vbias=VDD, Vctrl-Vbias=-VDD; when Vctrl is a logic high level (take 2.5V as an example), the first The enhancement FET transistor is turned on, Vbias=second resistance / (first resistance+second resistance)*VDD, Vctrl-Vbias=Vctrl-second resistance / (first resistance+second resistance)*VDD, under normal circumstances , Vctrl-Vbias should be greater than the turn-on voltage Vt. If VDD fluctuates greatly or Vctrl decreases, it may cause Vctrl-Vbias to be less than the turn-on voltage Vt, thereby turning off the switch tube and generating a wrong working state
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[0019] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.
[0020] In order to understand the above objects, features and advantages of the present invention more clearly, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features of the embodiments may be combined with each other unless there is conflict.
[0021] Many specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can also be implemented in other ways different f...
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The invention relates to a Bypass switch bias voltage generating circuit. Wherein the grid electrode of the first enhancement mode FET transistor is connected with the control voltage and the grid electrode of the second enhancement mode FET transistor, the source electrode of the first enhancement mode FET transistor is grounded, and the drain electrode of the first enhancement mode FET transistor is connected with the second resistor. The grid electrode of the second enhancement mode FET is connected with the control voltage and the grid electrode of the first enhancement mode FET, the drain electrode is connected with the grid electrode of the second enhancement mode FET, and the source electrode is connected with the third resistor. The upper end of the first resistor is connected with power voltage VDD, and the lower end is connected with bias voltage. The upper end of the second resistor is connected with the third resistor and the bias voltage, and the lower end of the second resistor is connected with the drain electrode of the first enhanced FET transistor. The lower end of the third resistor is connected with the second resistor, and the upper end of the third resistor is connected with the source electrode of the second enhanced FET transistor. The control voltage Vctrl controls the on-off of the first enhancement mode FET transistor, and the second enhancement mode FET transistor and the third resistor form a one-way voltage follower.
Description
technical field [0001] The invention belongs to the field of modern wireless communication technology, and in particular relates to a bypass switch bias voltage generating circuit. Background technique [0002] In modern wireless communication system receivers, in order to resist the adverse effects of channel saturation or signal compression or even device damage that may be caused by large signal input, it is required that the low-noise amplifier chip must be able to directly lead the large signal at the input end to the output end, that is, Bypass functions such as figure 1 shown. like figure 2 As shown, it includes a depletion mode (D-mode) FET transistor, first and second resistors and first and second capacitors, signal input and output terminals, control voltage and bias voltage. The gate of the first depletion FET transistor is connected to the first resistor, the source is connected to the first capacitor and the second resistor, and the drain is connected to th...
Claims
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Login to View More IPC IPC(8): G05F1/56
CPCG05F1/561Y02B70/10
Inventor 项勇戈泽宇陈浪陈力生
Owner 苏州悉芯射频微电子有限公司