Method and equipment for creating time delay table of FPGA (Field Programmable Gate Array) circuit and obtaining time delay

Abstract

The embodiment of the invention provides a method for creating a time delay table of an FPGA (Field Programmable Gate Array) circuit and a method and equipment for acquiring time delay, the FPGA circuit comprises a plurality of Slices, the time delay table comprises an internal time delay table, and the method comprises the following steps: determining a plurality of lines from an input pin to an output pin in each Slice in the plurality of Slices; calculating internal time delays from the input pin to the output pin based on the plurality of lines; and storing the input pin and the output pin corresponding to the plurality of lines of each Slice and the corresponding internal time delay between the two pins in an internal time delay table. According to the technical scheme provided by the embodiment of the invention, the estimation of the total time delay can be more accurate, so that the FPGA circuit designed or optimized based on the estimation can meet the time sequence constraint.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, and in particular, to a method and device for creating a delay table of a Field-Programmable Gate Array (FPGA) circuit and acquiring the delay of an FPGA circuit. Background technique [0002] The design process of an FPGA chip mainly includes design input, functional simulation, logic synthesis, technology mapping, logic packaging, layout, routing, timing simulation, bitstream generation and other stages. Among them, the physical implementation stages such as logic packaging, layout, and wiring are very complex. and a critical stage, the results of which directly affect circuit performance, area, reliability, power, and manufacturing yield. [0003] With the advancement of the manufacturing process, the parasitic parameters (such as parasitic capacitance, resistance, and inductance) of the connection lines in the FPGA chip are increasing, and the time delay of the connection lines is...

AI Technical Summary

Problems solved by technology

[0003] With the progress of the manufacturing process, the parasitic parameters (such as parasitic capacitance, resistance, and inductance) of the connection lines in the FPGA chip are increasing, and the delay of the connection lines is also increasing, making it difficult for the design of the FPGA circuit to meet the timing constraints.

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