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Semiconductor structure based on ferroelectric Schottky tunnel junction and preparation method thereof

A semiconductor and ferroelectric technology, applied in the direction of semiconductor devices, electric solid devices, circuits, etc., can solve the two-way signal feedback behavior and system disorder, do not have high energy efficiency and high stability ultra-large-scale storage and computing integrated neuromorphic chips, related devices Structurally limited resistive bidirectional conduction working mode and other issues, to achieve the effect of large current switching ratio, stable switching state storage, and large on-state current

Pending Publication Date: 2022-07-08
西安电子科技大学杭州研究院
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the structure of related devices is limited by the resistive bidirectional conduction mode, which leads to the signal bidirectional feedback behavior and system disorder of multi-level neurons in complex neural networks. Morphology Chip Capabilities

Method used

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  • Semiconductor structure based on ferroelectric Schottky tunnel junction and preparation method thereof
  • Semiconductor structure based on ferroelectric Schottky tunnel junction and preparation method thereof
  • Semiconductor structure based on ferroelectric Schottky tunnel junction and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0091] Schottky tunneling junction based on HZO ferroelectric material was fabricated on Si substrate.

[0092] Step 1: Select Substrate and Grow Dielectric Spacer.

[0093] Select Si as the substrate 100 and SiO in turn 2 As the SOI substrate composed of the first isolation layer 200 and Si as the channel layer 300, such as figure 2 shown; a sacrificial layer with a thickness of 8 nm is grown by chemical vapor deposition process, and the resulting structure is as follows image 3 shown.

[0094] Step 2: Ion implantation.

[0095] Photolithography of the sacrificial layer, and then use of ion implantation process, using P - As the ion source, set the ion implantation energy to 20KeV, start the implantation from the surface of the sacrificial layer, and the carrier concentration in the doped region is 1×10 18 cm -3 , the resulting structure is Figure 4 shown.

[0096] Step 3: forming the first electrode layer 400 and the second electrode layer 500 .

[0097] Using ph...

Embodiment 2

[0103] Schottky tunneling junction based on HAO ferroelectric material was fabricated on Ge substrate.

[0104] Step 1: Select Substrate and Grow Dielectric Spacer.

[0105] Select Ge as the substrate 100 and SiO in turn 2 As the GOI substrate composed of the first isolation layer 200 and Si as the channel layer 300, such as figure 2 shown; a sacrificial layer with a thickness of 8 nm is grown by chemical vapor deposition process, and the resulting structure is as follows image 3 shown.

[0106] Step 2: Ion implantation.

[0107] Photolithography of the sacrificial layer, and then use of ion implantation process, using P - As the ion source, set the ion implantation energy to 15KeV, start the implantation from the surface of the sacrificial layer, and the carrier concentration of the doped region is 1×10 18 cm -3 , the resulting structure is Figure 4 shown.

[0108] Step 3: forming the first electrode layer 400 and the second electrode layer 500 .

[0109] Using ph...

Embodiment 3

[0115] Schottky tunneling junction based on HfSiO ferroelectric material was fabricated on Si substrate.

[0116] Step 1: Select Substrate and Grow Dielectric Spacer.

[0117] Select Si as the substrate 100 and SiO in turn 2 As the SOI substrate composed of the first isolation layer 200 and Si as the channel layer 300, such as figure 2 shown; a sacrificial layer with a thickness of 8 nm is grown by chemical vapor deposition process, and the resulting structure is as follows image 3 shown.

[0118] Step 2: Ion implantation.

[0119] Photolithography of the sacrificial layer, and then use of ion implantation process, using P - As the ion source, set the ion implantation energy to 20KeV, start the implantation from the surface of the sacrificial layer, and the carrier concentration in the doped region is 1×10 18 cm -3 , the resulting structure is Figure 4 shown.

[0120] Step 3: forming the first electrode layer 400 and the second electrode layer 500 .

[0121] Using ...

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Abstract

The invention relates to a semiconductor structure based on a ferroelectric Schottky tunnel junction. The semiconductor structure comprises a substrate; the first isolation layer is arranged on the upper surface of the substrate; the channel layer is arranged on the upper surface of the first isolation layer and comprises an intrinsic region and a doped region, and the upper surface of the doped region is flush with the upper surface of the channel layer; the first electrode layer is arranged on the upper surface of the intrinsic region; the second electrode layer is arranged on the upper surface of the doped region; the ferroelectric layer is arranged between the first electrode layer and the second electrode layer and covers part of the upper surface of the first electrode layer; and the third electrode layer is arranged on the upper surfaces of the ferroelectric layer and the second electrode layer. According to the semiconductor structure, the excellent one-way conduction characteristic of the ferroelectric Schottky tunnel junction is utilized, and the ferroelectric layer is used for controlling the width of the ferroelectric Schottky tunnel junction to realize switching and storage of a device, so that switching control has good nonvolatile impedance characteristic and one-way conductivity.

Description

technical field [0001] The invention relates to the field of microelectronic devices, in particular to a semiconductor structure based on a ferroelectric Schottky tunnel junction and a preparation method thereof. Background technique [0002] With the advent of the era of "Internet of Everything and Intelligence of Everything", people have an urgent need for intelligent applications in various fields, and the existing artificial intelligence technology and corresponding hardware can no longer meet the needs of the times. As an important hardware support for neuromorphic computing technology, neuromorphic chips with integrated storage and computing not only have brain-like functions such as large-scale parallel processing, self-organization, and self-learning, but also break through the "storage wall" of Feng's architecture through distributed storage and computing structures. It has irreplaceable application prospects in the fields of comprehensive information processing tha...

Claims

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Application Information

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IPC IPC(8): H01L27/1159H01L29/47
CPCH01L29/47H10B51/30
Inventor 刘艳周久人闫钦元冯雯静郑思颖韩根全郝跃
Owner 西安电子科技大学杭州研究院