Parameter extraction modeling method suitable for discrete device after scribing

Abstract

The invention relates to a parameter extraction modeling method suitable for a discrete device after scribing. The method comprises the steps that a left side bonding pad, a to-be-tested device after scribing and a right side bonding pad are connected into a GSG on-chip testing structure in a gold wire bonding mode; capacitive compensation parameters of the left side compensation network and the right side compensation network caused by the left side bonding pad and the right side bonding pad are obtained through measurement; respectively determining inductive compensation parameters of left and right side compensation networks caused by gold wires bonded by gold wires based on the straight-through distances between the left and right side bonding pads and the to-be-tested device; determining S parameters of the left and right side compensation networks according to the inductive compensation parameters and the capacitive compensation parameters of the left and right side compensation networks; and respectively adding the S parameters of the compensation networks on the left side and the right side to the input end and the output end of test calibration compensation data of the vector network analyzer so as to remove the wiring influence of the GSG on-chip test structure. According to the method, the accurate large signal model can be quickly and effectively obtained, and model change caused by inter-chip non-uniformity of a device process is avoided.

Description

technical field [0001] The invention relates to the technical field of on-chip testing, in particular to a parameter-raising modeling method suitable for discrete devices after dicing. Background technique [0002] With the development and application of radio frequency devices, especially wide bandgap compound semiconductor devices, the operating frequency of the circuit is increased, and the output power is larger, especially the requirement for efficiency is accurate to 1%, so the power amplifier circuit, especially the mixed power The design of the amplifying circuit has higher and higher requirements on the model. [0003] Device models are the basis of circuit design. Power amplifier circuit design relies on accurate device models, especially nonlinear large-signal models. An accurate device model can significantly shorten the circuit design cycle, improve the design success rate, and reduce costs. [0004] In addition to the traditional silicon-based LDMOS and GaAs-b...

AI Technical Summary

Problems solved by technology

[0004] In addition to the traditional silicon-based LDMOS and GaAs-based pHEMT, currently used RF power devices, gallium nitride (GaN) devices with higher power density are more and more widely used, but the large-signal model of these new material devices It is not yet mature, and the failure analysis of new materials, the defect structure is not clear, and there is still room for improvement in the process, which leads to the accuracy of the model not meeting the design requirements, especially for uniformity between sheets and dimensional diversity. The reason is that we need to adjust the die size in real time when we select the die size in the circuit design, and the commercial die has no connection form that can be tested on the chip, and only one-to-one testing can be performed through external circuits and bonding wires.

Images