Network-on-chip incremental task mapping method for load balancing

Abstract

The invention discloses a network-on-chip incremental task mapping method for load balancing, which comprises the following steps of: firstly, inputting load information and incremental tasks mapped to each PE (Provider Edge) by an original function, and after the information is input, carrying out incremental mapping mainly in three stages, including a sorting stage, a maximum parallel set task allocation stage and a final allocation stage. According to the method and the system, the tasks are distributed in a mode of respectively carrying out priority ranking on the tasks and the PEs, so that NoC platform resources are utilized more fully, the task parallel processing capability of the NoC platform is fully scheduled, the task execution efficiency of the NoC platform is improved, the inter-core communication on the NoC platform is reduced, and the delay and the power consumption of a system for processing the tasks are effectively reduced. Besides, the load balancing of the NoC platform can be effectively realized, so that congestion is prevented as far as possible, communication hotspots are reduced, and mapping decisions are made for distribution and execution of specific incremental tasks, so that the system performance is more excellent, and the potential of the platform is fully played.

Description

technical field [0001] The invention relates to the field of incremental task mapping, in particular to an on-chip network incremental task mapping method for load balancing. Background technique [0002] With the rapid development of integrated circuit technology, Multi-processor System-on-Chip (MPSoC) will integrate hundreds of cores in a single chip to provide high throughput, low latency and low energy consumption to meet the needs of various an actual functional requirement. Due to the increased bus load and reduced network communication performance of the traditional bus interconnect structure of MPSoC, the bus structure is no longer suitable for the interaction between multiple cores. of the art", D. Belkebirand A. Zga, 2019 International Conference on Networking and Advanced Systems (ICNAS), 2019, pp. 1-6), as a new technology for high-speed communication between multiple cores, Network-on-Chip (Network- on-Chip, NoC) is proposed to meet the increasing communicatio...

AI Technical Summary

Problems solved by technology

However, the power consumption of transistors cannot be reduced with the limitation of leakage power, which leads to the failure of Dennard Scaling and the arrival of the dark silicon era

Therefore, under the limitation of power consumption, SoC faces the challenge of how to design an efficient NoC mapping algorithm to make full use of NoC computing and storage resources

In addition, the energy consumption of NoC increases with the increase of latency, which is closely related to the communication total Manhattan distance and transmission path congestion

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