Wafer-level system packaging structure and packaging method

A system packaging and wafer-level technology, applied in the direction of manufacturing microstructure devices, processing microstructure devices, TV system components, etc., can solve the problems of low packaging efficiency, improve packaging efficiency, simplify the process flow, and prevent horizontal spillover effect

Inactive Publication Date: 2022-07-29
NINGBO SEMICON INT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The invention discloses a wafer-level system packaging structure an

Method used

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  • Wafer-level system packaging structure and packaging method
  • Wafer-level system packaging structure and packaging method
  • Wafer-level system packaging structure and packaging method

Examples

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Embodiment 1

[0035] This embodiment provides a wafer-level system packaging method, including the following steps:

[0036]S01: Provide a first device wafer, a plurality of first device modules are formed inside the first device wafer, the first device wafer has a front surface and a back surface, the front surface is exposed to electrically connect the first device a plurality of first pads of the module and recessed on the front surface;

[0037] S02: Provide a second device wafer, a plurality of second device modules are formed inside the second device wafer, the second device wafer includes opposite upper and lower surfaces, and the upper surface exposes electrical connections the second device module and a plurality of second pads recessed on the upper surface;

[0038] S03: bonding the first device wafer and the second device wafer, so that the first pad and the second pad are relatively surrounded by a gap;

[0039] S04: Use an electroplating process to form conductive bumps in th...

Embodiment 2

[0066] refer to Figure 5 The difference between this embodiment and Embodiment 1 is that the back of the first device module 201 has a first electrical connection structure 22, and before or after cutting the first device wafer 20, a first chip 50 or a third device wafer is provided, The first chip 50 or the third device wafer is electrically connected to the first electrical connection structure 22 .

[0067] In this embodiment, the first electrical connection structure 22 is formed on the back of the first device module 201 . After the first device wafer is cut, the first chip 50 is provided; then the first chip 50 is bonded to the first device module 201 . combine. The first chip 50 may be electrically connected to one first device module 201 , or may be electrically connected to two or more first device modules 201 . The figure shows a situation in which the first chip 50 is electrically connected to one first device module 201 . It should be noted that, to electricall...

Embodiment 3

[0070] refer to Image 6 The difference between this embodiment and Embodiment 2 is that the lower surface of the second device module 101 has a second electrical connection structure 13, and the method further includes: providing a second chip or a fourth device wafer 100, The second chip or the fourth device wafer 100 is electrically connected to the second electrical connection structure 13 .

[0071] The lower surface of the second device module 101 has a second electrical connection structure 13 , the fourth device wafer 100 includes a plurality of second chips 51 , and the second electrical connection structure 13 is electrically connected to the second chips 51 . First, the lower surface of the second device wafer 10 is thinned to expose the second electrical connection structure 13 , and then the fourth device wafer 100 is bonded on the second device wafer 10 , and the second chip 51 is connected to the second device wafer 10 . For the electrical connection of the sec...

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Abstract

The invention provides a wafer-level system packaging structure and method, and the method comprises the steps: providing a first device wafer which is internally provided with a plurality of first device modules, and is provided with a front surface and a back surface, a plurality of first welding pads which are electrically connected with the first device module and are sunken in the front surface are exposed out of the front surface; a second device wafer is provided, a plurality of second device modules are formed in the second device wafer, the second device wafer comprises an upper surface and a lower surface which are opposite to each other, and a plurality of second welding pads which are electrically connected with the second device modules and are recessed in the upper surface are exposed out of the upper surface; bonding the first device wafer and the second device wafer to enable the first welding pad and the second welding pad to oppositely enclose a gap; and forming a conductive bump in the gap by adopting an electroplating process so as to electrically connect the first welding pad and the second welding pad.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a wafer-level system packaging structure and packaging method. Background technique [0002] System-in-package uses any combination to combine multiple active components / devices, passive components / devices, MEMS devices, discrete KGD (Known Good Die) with different functions and prepared by different processes, such as optoelectronic chips, biochips, etc., It is integrated and assembled in three dimensions (X direction, Y direction and Z direction) into a single standard package with a multi-layer device structure and can provide multiple functions to form a system or subsystem. [0003] Flip-chip (FC, Flip-Chip) soldering is a commonly used system-in-package method at present. The system-in-package method includes: providing a PCB circuit board, wherein solder balls arranged according to certain requirements are formed on the PCB circuit board (formed by a ball-mounting p...

Claims

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Application Information

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IPC IPC(8): H01L21/60H01L21/78B81B7/00B81B7/02B81C1/00B81C3/00H05K1/18H05K3/34
CPCH01L24/83H01L24/81H01L24/11H01L24/97H01L24/32B81C1/00095B81C1/00261B81C3/001B81B7/02B81B7/0032B81B7/0006B81C1/00888H05K1/181H05K3/3436H01L2224/32238H01L2224/11462H05K2201/037H01L2224/81H01L2224/96H01L2924/181H01L2924/00012
Inventor 黄河向阳辉刘孟彬
Owner NINGBO SEMICON INT CORP
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