Non-volatile semiconductor memory unit with separate bit line structure

Abstract

A non-volatile semiconductor memory cell with a split bit line structure, the main bit line is controlled by at least one bit line selection component to transmit its potential to the selected secondary bit line, so that the memory cell transistors in the selected section Therefore, it can avoid the bit line load (BL Loading) generated by the parasitic capacitance. Then, the memory cell transistor and the bit line selection component are respectively designed in the side-by-side P well and N well, which can further avoid programming (writing) bit line interference or erasing bit line interference.

Description

technical field [0001] The present invention relates to a semiconductor storage unit, and in particular to a non-volatile semiconductor storage unit with a split bit line structure. Background technique [0002] In non-volatile memory, the reason why the flash storage unit can be programmed (Program), mainly uses various operation methods (such as Channel Hot Electron Injection (Channel Hot Electron Injection), FN tunneling effect (Fowler-Nordheim tunneling), etc.) Writing to the floating gate increases the threshold voltage of memory storage cells. As for erasing (Erase), electrons are pulled out from the floating gate to lower the critical voltage of the memory storage unit. [0003] like Figure 1A and Figure 1B Respectively, the structure diagram and circuit diagram of the bit line connection mode of ordinary flash memory, by Figure 1A It can be seen that an N-type substrate 10, a deep P well 12, and an N well region 14 are sequentially formed in the flash memory fro...

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Problems solved by technology

[0006] The above programming (writing) bit line interference or erasing bit line interference will directly affect the data storage capacity of the memory storage unit, resulting in data loss. In addition, the bit line is connected to the source and the source of each memory storage unit. The P-type ion region (or called shallow P well region (Shallow P-well)), will form a parasitic capacitance at the source terminal (such as Figure 1B 32), so when reading, these capacitors will cause a larger bit line load (BL Loading), thus reducing the reading speed

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