Semiconductor memory device

A storage device and semiconductor technology, which is applied in the fields of semiconductor devices, information storage, and semiconductor/solid-state device manufacturing, etc., can solve problems such as a decrease in the qualification rate and an increase in the number of manufacturing processes.

Inactive Publication Date: 2006-07-05
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0015] In addition, at the same time, with the addition of charging capacity for cell nodes, the number of manufacturing steps increases, and there is a problem that the yield rate decreases due to the increase in the number of steps.

Method used

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  • Semiconductor memory device
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Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0059] figure 1 (a) and (b) are circuit diagrams of a typical all-CMOS type memory cell of a type in which charge capacity is added to a cell node for countermeasures against soft errors. figure 1 The two circuits shown in (a) and (b) are equivalent circuits, in figure 1 In (a), each component is arranged corresponding to the actual structure of the horizontally long memory cell, and on the other hand, in figure 1 In (b), each component is arranged according to the principle of simplifying and clarifying the circuit diagram.

[0060] The memory cell 10 has a general six-transistor unit structure, and has a first p-type large-capacity load transistor (hereinafter referred to as the first load transistor) 3 and a second p-type large-capacity load transistor (hereinafter referred to as the second load transistor) 4 as transistors. , 1n-type large-capacity driving transistor (hereinafter referred to as the first driving transistor) 5, 2n-type large-capacity driving transisto...

Embodiment approach 2

[0100] Figure 8 is a plan view of each stage of the manufacturing process of the full CMOS memory cell according to Embodiment 2 of the present invention, Figure 8 (a) and (b) respectively with figure 2 (c) and (e) correspond. In the first embodiment described above, the case where the power supply voltage (Vdd) is applied to the conductive film 15 constituting the charging capacity body is described, but the present invention is not limited to this, and a ground voltage may be applied to the conductive film constituting the charging capacity body. (Vss), the potential of the conductive film is equal to the potential of the sources of the first and second driving transistors 5 and 6. In this case, if Figure 8 As shown in (a), a sufficient margin can be maintained between the conductive film 35 and the mosaic wiring 13B, 13C, 13D, 13G, 13H, and 13I connected to each power supply voltage line or bit line without contact. On the other hand, the interval between the conduc...

Embodiment approach 3

[0107] Figure 13 (a) to (f) are diagrams showing respective states during formation of cell nodes and charging capacity bodies included in the memory cell according to Embodiment 3 of the present invention. In this Embodiment 3, the difference from the above-mentioned Embodiment 1 is that, after forming the trench for wiring and the concave portion communicating with the trench for wiring, they are buried simultaneously. A technique for forming cell nodes and charge capacitors (so-called dual damascene processing). exist Figure 13 In the state shown in (a), the etching stopper film 23 is formed after the active layers 11A, 11B, 11C, and 11D are formed, as in the case of Embodiment 1 described above. From this state, such as Figure 13 As shown in (b), the planarization insulating film 24 is formed on the entire surface, and then the etching stopper layer 41 and the planarization insulating film 42 are deposited.

[0108] Thereafter, the planarization insulating film 42 o...

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Abstract

The invention provides a semiconductor memory device which is excellent in soft error resistance by adding a charge capacity to a cell node without increasing a cell area. In a semiconductor memory device with a full CMOS type memory cell, which has two n-type bulk access transistors and two n-type bulk driver transistors and two p-type bulk load transistors, respectively, a charge capacity body for charge capacity addition connected to a storage node is constituted of an insulation film and a conductive film, and the insulation film and the conductive film are formed directly on an upper side of the first and second cell nodes.

Description

technical field [0001] The present invention relates to semiconductor memory devices. Background technique [0002] With the integration of ICs and the development of lower voltage, the amount of charge held during storage in semiconductor storage devices has decreased. Along with this, there is a tendency for electric charges held during storage to occur in semiconductor storage devices. The tendency of the phenomenon that the positive or negative of the signal is changed by the influence of radiation such as α-ray and leakage current (so-called soft error). Therefore, in recent years, a semiconductor memory device having excellent resistance to soft errors while achieving integration and lower voltage has been demanded. [0003] In connection with this, in a static RAM (hereinafter referred to as SRAM) in which written data is stored while maintaining power supply, generally H The storage node on the side is connected to a power supply with very low impedance, and theref...

Claims

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Application Information

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IPC IPC(8): H01L27/11H01L21/8244G11C11/412
CPCG11C11/412G11C11/4125H01L27/1104H01L27/11H10B10/00H10B10/12
Inventor 大林茂树石垣佳之横山岳宏
Owner MITSUBISHI ELECTRIC CORP
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