Silicon/germanium-silicon vertical nodded type field effect transistor

Abstract

A junction field effect transistor and method for making is described incorporating horizontal semiconductor layers within an opening to form a channel and a semiconductor layer through which the opening was made which forms a gate electrode surrounding the channel. The horizontal semiconductor layers may be a SiGe alloy with graded composition near the source and drain. The invention overcomes the problem of forming low resistance JFET's and provides a gate length that is easily scaleable to submicron dimensions for rf, microwave, millimeter and logic circuits without short channel effects.

Description

field of invention [0001] This invention relates to junction field effect transistors, and more particularly to junction field effect transistors with a vertical channel of a graded SiGe alloy that provides strain for increased mobility and provides An induced electric field accelerates the charge carriers into the channel. technical background [0002] In standard metal-oxide-silicon (MOS) processes, enhancements in the speed of field effect transistors are usually accompanied by a reduction in device size. However, when the gate length of the transistor is less than 0.1 micron or less, there is a size limit because various other parameters cannot be scaled down. Short channel effects become important, but also inertial effects that cause carriers (electrons) to move at a low speed at the source of the channel become important. [0003] In US Patent 5,019,882, issued May 28, 1991 to P.M. Solomon, a field effect transistor containing a layer of silicon germanium used as a ...

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Problems solved by technology

However, when the gate length of the transistor is less than 0.1 microns or less, there is a size limit because various other parameters cannot be scaled down

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