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Semiconductor device and method of manufacturing the same

A technology for semiconductors and devices, applied in the field of semiconductor devices with contact holes and their manufacturing, can solve the problems of not reducing wiring capacitance, complex manufacturing processes, and many processes, and achieve easy forming processes, simplifying manufacturing processes, and reducing Effects of Bit Line Routing Capacitance

Inactive Publication Date: 2006-12-27
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0025] However, compared with the self-aligned opening method using a silicon nitride film stopper, the above-mentioned diameter reduction process has problems in that the number of steps is large and the manufacturing process is complicated.
In addition, as the size of the memory cell is reduced, the contact diameter of the contact hole 161 for capacitors is also required to be reduced. It's getting more and more difficult technically
However, the outer diameter used for the vertical portion 112a is small, so the degree of reduction of the bit line wiring capacitance between adjacent bit lines 110a is not achieved.

Method used

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  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0094] figure 1 It is a cross-sectional structure diagram showing a DRAM according to Embodiment 1 of the present invention. refer to figure 1, in the memory cell portion of the DRAM of this embodiment, the separation region 2 is formed in a prescribed region of the main surface of the silicon substrate 1 . The separation region 2 is formed such that the oxide film is buried in the trench after the trench is formed. The separation area can also use the usual LOCOS separation oxide film. Source / drain regions 6a, 6b, and 6c are formed at predetermined intervals in the active region surrounded by isolation region 2 . Gate electrode 4a is formed through gate oxide film 3 on the channel region located between source / drain regions 6a and 6b. Furthermore, gate electrodes 4b and 4c are formed at a predetermined interval from the gate electrode 4a.

[0095] A TEOS oxide film 5 is formed on the upper surfaces of the gate electrodes 4a, 4b, and 4c. Further, TEOS oxide film 7 is for...

Embodiment 2

[0122] Figure 21 It is a sectional view showing a DRAM according to Embodiment 2 of the present invention. refer to Figure 21 , in the DRAM of the second embodiment, the plug electrode 13 and the bit line 16a have the same structure as that of the first embodiment. However, in this second embodiment, the structure of the capacitor is different from that of the first embodiment.

[0123] Specifically, in the structure of the second embodiment, the capacitor lower electrode portion 43b is not directly connected to the upper surface of the plug electrode 13 , and the capacitor contact portion 43a is interposed between the capacitor lower electrode portion 43b and the plug electrode 13 . The capacitor contact portion 43a is integrally formed with the capacitor lower electrode portion 43b.

[0124] Further, a silicon nitride film 21a is formed on the upper surface of the interlayer insulating film 11 and on the upper surface of the TEOS oxide film 17a. Furthermore, an interla...

Embodiment 3

[0140] Figure 31 It is a cross-sectional view showing a DRAM according to Embodiment 3 of the present invention. refer to Figure 31 , In this third embodiment, the capacitor lower electrode 54a is made into a simple laminated structure instead of the cylindrical structure of the above-mentioned embodiments 1 and 2. In addition, the surface of the capacitor lower electrode 54a is roughened with unevenness. Thereby, the surface area of ​​the capacitor lower electrode 54a is increased, and as a result, the capacitance of the capacitor can be increased. Furthermore, a capacitor upper electrode 57a is formed on the capacitor lower electrode 54a with the capacitor dielectric film 56 interposed.

[0141] The capacitor lower electrode 54a having irregularities on the surface is formed by the method described below. That is, in high vacuum (~10 -6 Torr) by flowing through disilane (Si 2 h 6 ) or silane (SiH 4 ) gas to selectively grow polysilicon grains on the polysilicon fil...

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Abstract

A semiconductor device is obtained which allows a simpler formation process of a capacitor contact hole and reduction in capacitance between bit interconnections. A first capacitor contact hole is formed in a silicon nitride film and an interlayer insulating film in which a bit line contact hole is formed. The first capacitor contact hole is filled with a plug electrode having its top surface area larger than its bottom surface area. A capacitor lower electrode is formed to be connected to the top surface of the plug electrode and to cover the side and top surfaces of a bit line with a sidewall oxide film and a TEIS oxide film located there between.

Description

technical field [0001] The present invention generally relates to semiconductor devices and methods of manufacturing the same, and more particularly, to semiconductor devices having contact holes and methods of manufacturing the same. Background technique [0002] Heretofore, DRAM (Dynamic Random Access Memory) is known as one type of semiconductor memory of a semiconductor device. FIG. 35 is a cross-sectional view showing a conventional DRAM. Referring first to FIG. 35, the cross-sectional structure of a conventional DRAM will be described. [0003] In a memory cell portion of a conventional DRAM, a separation region 102 is provided in a predetermined region on the main surface of a silicon substrate 101 . In addition, source / drain regions 106 a , 106 b , and 106 c are formed in the active region surrounded by the separation region 102 . Gate electrode 104a is formed through gate oxide film 103 on the channel region between source / drain regions 106a and 106b. Furthermor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/108H01L21/8242H01L23/522H01L21/768H01L29/78H10B12/00
CPCH01L27/10852H01L27/10817H10B12/318H10B12/033H10B12/00
Inventor 新川田裕树
Owner MITSUBISHI ELECTRIC CORP