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Method for manufacturing semiconductor device

A manufacturing method and semiconductor technology, which are applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of small contact hole diameter, inability to completely remove the CuO film, and inability to adequately clean

Inactive Publication Date: 2004-08-04
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, especially in a miniaturized semiconductor device, due to the small diameter of the contact hole, sufficient cleaning is not possible, and the reality is that the CuO film 140 cannot be completely removed.

Method used

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  • Method for manufacturing semiconductor device
  • Method for manufacturing semiconductor device
  • Method for manufacturing semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0082] Figure 1 to Figure 6 It is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1 of the present invention in order of steps. The manufacturing method of the semiconductor device of the present embodiment 1 is aimed at the semiconductor device with multilayer copper wirings discussed in the description of the prior art. Figure 1 to Figure 6 In , a method of forming a unit of wiring layers in such a semiconductor device is shown. Since the method of forming the semiconductor element existing under the TEOS film 1 is the same as the conventional method, description thereof will be omitted. Thus, in Figure 1 to Figure 6 In , the description of the semiconductor substrate, MOS transistor, element isolation insulating film, interlayer insulating film, etc. existing under the TEOS film 1 is omitted.

[0083] First, the TEOS film 1 is formed by a CVD method or the like. Next, according to the CVD method or the PVD m...

Embodiment 2

[0098] Figure 7 ~ Figure 14 It is a cross-sectional view showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention in order of steps. In these figures, with Figure 1 to Figure 6 Likewise, descriptions of the semiconductor substrate, MOS transistors, element isolation insulating films, interlayer insulating films, etc. existing under the TEOS film 1 are omitted.

[0099] First, according to the CVD method or the PVD method, the TEOS film 1, the FSG film 2, and the silicon nitride oxide film 50 are sequentially formed ( Figure 7 ). However, instead of forming the silicon oxynitride film 50 , the same rare gas atom-containing layer 3 and silicon carbide film (SiC) as in the first embodiment described above may be formed.

[0100] Next, after forming a resist having a predetermined pattern of openings on the silicon oxynitride film 50, the silicon oxynitride film 50 and the FSG film 2 are anisotropically dry-etch...

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Abstract

To provide a producing method for a semiconductor device, with which wiring capacity between adjacent wiring can be reduced. After a TEOS film 1 is formed, an FSG film 2 is formed on the TEOS film 1 by a CVD method or PVD method. Further, the CVD or PVD of the FSG film is continued so that rare gas atoms can be taken into the film and a rare gas atom containing layer 3 is formed. Next, the rare gas atom containing layer 3 and the FSG film 2 are etched in this order while using a resist 4, which is formed on the rare gas atom containing layer 3, for a mask. Next, after the resist 4 is removed, a barrier metal and a copper film 7 are formed over all the surface. Next, the copper film 7 and the barrier metal 6 are ground and removed in this order by a CMP method until the upper surface of the rare gas atom containing layer 3 is exposed. Thus, as a copper film 7 remaining without being ground, copper wiring 9 for filling a groove 5 is formed.

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a metal wiring using a CMP (Chemical Mechanical Polishing) method. Furthermore, the present invention relates to a semiconductor device manufactured according to the method described above. Background technique [0002] A semiconductor integrated circuit is constituted by a plurality of semiconductor elements formed on the main surface of a semiconductor substrate in an element formation region. The semiconductor elements are electrically isolated from each other by an element isolation insulating film such as STI (Shallow Trench Isolation) formed in the main surface of the semiconductor substrate in the element isolation region. In order to realize the function as a semiconductor integrated circuit, each semiconductor element is electrically connected to each other by conductors such as wiring. [0003] As the conductor, po...

Claims

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Application Information

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IPC IPC(8): H01L21/3205H01L21/304H01L21/768H01L23/52H01L23/532
CPCH01L21/76843H01L21/76802H01L21/76808H01L21/7684H01L2221/1036H01L21/76801H01L21/76814H01L21/76819H01L23/53238H01L21/76825H01L2924/0002H01L2924/00H01L21/3205
Inventor 国清辰也
Owner MITSUBISHI ELECTRIC CORP