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Method to relax alignment accuracy requirement in fabrication for integrated circuit

An integrated circuit, high-precision technology, applied in the direction of circuit, electrical components, semiconductor/solid-state device manufacturing, etc., to achieve the effect of increasing the margin

Inactive Publication Date: 2007-01-24
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to solve the defects existing in the method of alignment accuracy requirements of the existing integrated circuit manufacturing process, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time. This is obviously the relevant industry Urgent problem

Method used

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  • Method to relax alignment accuracy requirement in fabrication for integrated circuit
  • Method to relax alignment accuracy requirement in fabrication for integrated circuit
  • Method to relax alignment accuracy requirement in fabrication for integrated circuit

Examples

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no. 1 example

[0049] see Figure 3A As shown, a method for manufacturing a hard mask layer according to the first preferred embodiment of the present invention provides a substrate 100 and forms a layer of patterned mask layer 102 on the substrate 100 . The mask layer 102 has several openings 104 exposing the substrate 100 . The material of the mask layer is, for example, silicon oxide, and its formation method is, for example, to first form a layer of silicon oxide by chemical vapor deposition, and then pattern the silicon oxide layer by lithography and etching processes to form openings 104, wherein the openings 104a is one of the openings 104 . The size and shape of each opening 104 may be the same, or the same shape but different sizes, or different sizes and shapes. In addition, the formed openings 104 may be arranged in an array (array) or irregularly.

[0050] Next, see Figure 3B As shown, a buffer layer 106 is formed on the substrate 100 . The buffer layer 106 covers the surfa...

no. 2 example

[0062] The method of forming the mask layer 102 embedded with the buffer layer 106a of the present invention is not limited to the method described in the first embodiment, and it can also be formed by the method of the second embodiment. The second embodiment will cooperate with Figure 4A to Figure 4E to illustrate.

[0063] see Figure 4AAs shown, the method of the second embodiment provides a substrate 100, and forms several buffer layers 106a on the substrate 100, wherein the buffer layer 106b is one of the buffer layers 106a. Each buffer layer 106a may have the same size and shape, or the same shape but different size, or both size and shape. In addition, the formed buffer layers 106a may be arranged in an array or irregularly. The material of the buffer layer 106 a includes a suspension-coated material, such as a suspension-coated glass, or a metal, such as tungsten, titanium or titanium nitride. The buffer layer 106a can be formed by first forming a blanket buffer ...

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Abstract

A method to relax the alignment accuracy requirement in an integrate circuit manufacturing is described. The method comprises forming a mask layer over a substrate, and the mask layer comprises a plurality of first openings. Thereafter, a buffer layer fills the first opening, followed by forming a photoresist layer over the substrate. The photoresist layer is then patterned to form a second opening that corresponds to the first opening, and the second opening exposes a portion of the buffer layer. Isotropic etching is then performed to remove the buffer layer exposed by the second opening to expose a sidewall of the first opening that corresponds to the second opening. The photoresist layer is further removed to expose the mask layer that comprises the embedded buffer layer and the opening pattern, which is used as a hard mask layer in a subsequent process.

Description

technical field [0001] The invention relates to a method for manufacturing an integrated circuit, in particular to a method for reducing the alignment accuracy requirement of the integrated circuit manufacturing process. Background technique [0002] Lithography is one of the most important steps in semiconductor manufacturing. When the components are miniaturized, the alignment accuracy requirements will be higher, and the process margin will be reduced accordingly. In order to be able to align accurately, it is even necessary to use a more advanced and expensive lithography machine. [0003] For example, the prior art also faces the above-mentioned problems when making mask ROMs. see figure 1 What is shown is a schematic diagram of a conventional manufacturing method of a mask ROM. In the conventional manufacturing method of the mask ROM, a layer of pre-coding layer 20 is first formed on the substrate 10 when performing the encoding process of the mask ROM. The coding...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/82H01L21/033
CPCY10S438/942H01L21/0337H01L21/0332Y10S438/95
Inventor 钟维民
Owner MACRONIX INT CO LTD
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