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Production method of laminated base material with high integrated level

A manufacturing method and base material technology, applied in the direction of multi-layer circuit manufacturing, layered products, etc., can solve the problems of reducing the layout space of the circuit layer and the inability to effectively improve the circuit integration of the laminated base material.

Inactive Publication Date: 2003-02-05
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the via ring pad 102a and the via ring pad 102b usually reduce the layout space of the circuit layer, resulting in that the circuit integration in the build-up substrate cannot be effectively improved.

Method used

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  • Production method of laminated base material with high integrated level
  • Production method of laminated base material with high integrated level
  • Production method of laminated base material with high integrated level

Examples

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Comparison scheme
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no. 1 example

[0028] Figure 2A to Figure 2D It is a schematic cross-sectional view of the manufacturing process of the dielectric layer with patterned circuits in the build-up substrate according to the first embodiment of the present invention. The patterned circuit in the laminated substrate of this embodiment is formed by, for example, metal etching, patterned electroplating, semi-additive method, or full-additive method. In this embodiment, metal etching is used for illustration. First please refer to Figure 2A, providing a supporter 202 , and then forming a conductor layer 204 on the supporter 202 . Wherein, the material of the conductor layer 204 is, for example, copper, and the conductor layer 204 is formed on the support body 202 by, for example, sputtering, pressure bonding or deposition.

[0029] Then please also refer to Figure 2B and Figure 2C , and then form a patterned photoresist 206 on the conductor layer 204, the patterned photoresist 206 is used to define the patt...

no. 2 example

[0038] This embodiment is the same as the first embodiment in the fabrication of the dielectric layer with via holes and the pad opening layer, but the difference between this embodiment and the first embodiment lies in the dielectric layer with patterned lines way of making.

[0039] Figure 6A to Figure 6D It is a schematic cross-sectional view of the manufacturing process of the dielectric layer with patterned circuits in the build-up substrate according to the second embodiment of the present invention. First please refer to Figure 6A , providing a support body 602 , and then forming a conductor layer 604 on the support body 602 . Wherein, the material of the conductor layer 604 is, for example, copper, and the conductor layer 604 is formed on the support body 602 by, for example, sputtering, pressure bonding or deposition.

[0040] Then please also refer to Figure 6B and Figure 6C , and then forming a patterned photoresist 606 on the conductive layer 604 , the pat...

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Abstract

The lamination basis plate consists of stacked the multiple dielectric layers and the multiple circuit layers in turn. The dielectric layer possesses the multiple through holes. The circuit layers via the through hole are connected each other electrically. The characters of the basis plate are that the embedded type structure designof the ring pads with no through hole possessing better adhesive force and high reliability on the circuit layer is utilized instead of the traditional design of the ring pads with through hole. The invention also discloses the method for manufacturing the basis plate. After the dielectric layer with the pattern and the dielectric layer withthe through hles being prepared, the two kinds of the layers are aligned and prssed together so as to complete the procedure of manufacturing the basis plate.

Description

technical field [0001] The invention relates to a laminated substrate structure and a manufacturing method thereof, in particular to a packaging substrate or a printed circuit board structure and a manufacturing method thereof. Background technique [0002] Due to the progress and demand of electronic technology, various electronic related products are all developed in the direction of miniaturization and high density. In terms of packaging, the research and development of technologies such as Ball Grid Array (BGA) and Chip Scale Package (CSP) are aimed at the market's demand for miniaturized and high-density products. In terms of printed circuit boards, in order to reduce the circuit area of ​​the entire printed circuit board, the technology of multi-layer structure is also applied. However, no matter it is used for the substrate of the ball grid array package, the package in the chip size package, or the production of the printed circuit board (PCB), it is unavoidable to ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H05K3/46
Inventor 何昆耀宫振越
Owner VIA TECH INC
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